Patents by Inventor William Tuel

William Tuel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7810093
    Abstract: In a parallel computing environment comprising a network of SMP nodes each having at least one processor, a parallel-aware co-scheduling method and system for improving the performance and scalability of a dedicated parallel job having synchronizing collective operations. The method and system uses a global co-scheduler and an operating system kernel dispatcher adapted to coordinate interfering system and daemon activities on a node and across nodes to promote intra-node and inter-node overlap of said interfering system and daemon activities as well as intra-node and inter-node overlap of said synchronizing collective operations. In this manner, the impact of random short-lived interruptions, such as timer-decrement processing and periodic daemon activity, on synchronizing collective operations is minimized on large processor-count SPMD bulk-synchronous programming styles.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: October 5, 2010
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Terry R. Jones, Pythagoras C. Watson, William Tuel, Larry Brenner, Patrick Caffrey, Jeffrey Fier
  • Publication number: 20050131865
    Abstract: In a parallel computing environment comprising a network of SMP nodes each having at least one processor, a parallel-aware co-scheduling method and system for improving the performance and scalability of a dedicated parallel job having synchronizing collective operations. The method and system uses a global co-scheduler and an operating system kernel dispatcher adapted to coordinate interfering system and daemon activities on a node and across nodes to promote intra-node and inter-node overlap of said interfering system and daemon activities as well as intra-node and inter-node overlap of said synchronizing collective operations. In this manner, the impact of random short-lived interruptions, such as timer-decrement processing and periodic daemon activity, on synchronizing collective operations is minimized on large processor-count SPMD bulk-synchronous programming styles.
    Type: Application
    Filed: November 15, 2004
    Publication date: June 16, 2005
    Inventors: Terry Jones, Pythagoras Watson, William Tuel, Larry Brenner, Patrick Caffrey, Jeffrey Fier
  • Publication number: 20050078605
    Abstract: Messages arriving at a receiver are managed to ensure proper ordering of the messages. To facilitate proper ordering, a message sequence number is used, as well as matching criteria to match a correctly sequenced message with a posted receive. In response to processing a message, a check is made as to whether previously out of order messages can now be processed.
    Type: Application
    Filed: October 14, 2003
    Publication date: April 14, 2005
    Applicant: International Business Machines Corporaton
    Inventors: Su-Hsuan Huang, William Tuel