Abstract: Multi-spectral planar photodiode pixels are provided in accordance with the present invention for simultaneously detecting multi-colors of infrared radiation. Each multispectral planar photodiode pixel includes a semiconductor substrate layer, a buffer layer of a first conductivity type material deposited on a semiconductor substrate layer, and a first color layer of the first conductivity type material deposited on the buffer layer. The multispectral planar photodiode pixel further includes a barrier layer of the first conductivity type material deposited on the first color layer, a second color layer of the first conductivity type material deposited on the barrier layer, and a cap layer of the first conductivity type material deposited on the second color layer. A first diode comprising a second conductivity type material is formed in the first color layer, and a second diode comprising a second conductivity type material is formed in the second layer.

Abstract: A major difficulty with fabricating GaAs digital logic circuits using enhancement-mode MESFETs has been the large gate-source and gate-drain parasitic resistances inherent in conventional designs. A self-aligned gate process is presented, which incorporates a "mushroom" gate structure for self-aligning both an n+ implant and the source/drain contacts to the gate, thus minimizing the parasitic resistances. The "mushroom" gate consists of a two-layer TiW/Si metallization in which the bottom TiW layer is undercut with a closely controllable chemical etch. The process is compatible with the high temperature anneal necessary to activate ion-implanted GaAs.

Abstract: A method of fabrication for self-aligned gallium arsenide transistors using metal implant masks is disclosed. Preferred embodiments include use of a dummy gate (150) made of aluminum (144) on top of titanium tungsten (142) as an implant mask for source (52) and drain (54) formation with the titanium tungsten (142) undercut so that deposited silicon dioxide (62) will form a self-aligned mask for the gate deposition after the dummy gate (150) is removed.

Abstract: Bipolar transistors and other electronic structures are fabricated on a gallium arsenide (GaAs) substrate to form an integrated circuit device. This process is made possible by development of an ion implant technique which uses an acceptor material to create a P type region, boron or protons to create insulating regions, and silicon or selenium to create an N type region. The process avoids the difficult problems encountered in diffusion methods, and, due to the precise control available with the ion implant method, makes possible the fabrication of IC quality transistors consistently over a substrate. This same control enables the fabrication of integrated circuits with improved device packing density and reduced parasitic parameters.

Abstract: Bipolar transistors and other electronic structures are fabricated on a gallium arsenide (GaAs) substrate to form an integrated circuit device. This integrated circuit device is made possible by development of an ion implant technique which uses an acceptor material to create a P type region, boron or protons to create insulating regions, and silicon or selenium to create an N type region. The use of an ion implant technique avoids the difficult problems encountered in diffusion methods, and, due to the precise control available with ion implantation, makes possible the fabrication of IC quality transistors consistently over a substrate. This same control enables the fabrication of integrated circuits with improved device packing density and reduced parasitic parameters.