Abstract: Embodiments described herein provide a mechanism to use an on-chip buffer memory in conjunction with an off-chip buffer memory for interim NAND write data storage. Specifically, the program data flows through the on-chip buffer memory to the NAND memory, while simultaneously a copy of the NAND program data is buffered in one or more circular buffer structures within the off-chip buffer memory.

Abstract: A system and method for verifying an identifier of a command. The method includes receiving an incoming command and sending a first alert to auto-logging hardware, wherein the auto-logging hardware sends a fetch instruction in response to receiving the first alert; retrieving an identifier of the incoming command in response to the fetch instruction and sending a second alert to the auto-logging hardware, wherein the auto-logging hardware sends a search instruction in response to receiving the second alert; and searching for the identifier of the incoming command in a table in response to the search instruction, the table storing identifiers previously assigned to other commands, wherein the incoming command is logged into the search table and marked as a searched command after the search for the first identifier in the table has completed successfully.

Abstract: Apparatus having corresponding methods and computer-readable media comprise: a memory having a plurality of ports; a plurality of processors, wherein each processor is configured to access a respective port of the memory, and wherein each processor is configured to wait responsive to assertion of a respective wait signal; and an arbiter configured to assert the wait signals responsive to memory enable signals asserted by the processors such that the memory is accessed by only one of the processors at a time.

Abstract: A method and system for transferring frames from a storage device to a host system via a controller is provided. The method includes transferring frames from a transport module to a link module; and sending an acknowledgment to the transport module, wherein the link module sends the acknowledgement to the transport module and it appears to the transport module as if the host system sent the acknowledgement. The frames in the controller are tracked by creating a status entry indicating that a new frame is being created; accumulating data flow information, while a connection to transfer the frame is being established by a link module; and updating frame status as frame build is completed, transferred, and acknowledged. The controller includes, a header array in a transport module of the controller, wherein the header array includes plural layers and one of the layers is selected to process a frame.

Abstract: A controller and a method for interfacing between a host and storage medium. A storage medium interface includes CH0 circuitry for performing a CH0 process to access a buffer memory on behalf of the storage medium. A host interface includes CH1 circuitry for performing a CH1 process to access the buffer memory on behalf of the host. Access to the buffer memory is arbitrated in sequential tenures to each channel of the multi-channel bus within a maximum arbitration round trip time defined by the time taken by the storage medium to move a distance corresponding to N sectors in which N is greater than one. In the CH0 tenure, the CH0 process transfers data corresponding to N sectors of the storage medium in a multi-sector burst. The length of the tenure of the CH0 channel is pre-designated so that the multi-sector burst is completed within the CH0 tenure.

Abstract: A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.

Abstract: A storage controller includes a memory controller that interfaces with memory that stores data. A first receive logic interface provides an interface to a host. A second receive logic interface provides an interface to a storage device. A power save module has a power save mode in which at least a clock of the memory controller is turned off while a clock for operating the first receive logic interface and the second receive logic interface is kept on.

Abstract: A storage drive system including an interface and a channel. The interface is configured to i) receive frames from a host and ii) process the frames. The channel is configured to i) receive the frames from the interface and ii) transfer the frames from the interface to a buffer memory. The channel includes a first register configured to store bit values corresponding to frame processing, and includes a first module configured to i) detect frame types of the frames and ii) in response to detecting a first frame type, stop receiving a second frame type while selectively continuing to receive a third frame type based on the bit values.

Abstract: A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.

Abstract: Method and system for transferring data between a computing system and a storage device is provided. The system includes a storage controller including a frame snooper module that detects a TMR and generates a pause signal to a channel that stops the channel from sending any non-data frames to a buffer memory, wherein the channel continues to receive and process data frames while the channel is stopped from sending the command frames to the buffer memory; a counter for counting TMRs; and logic for generating an interrupt if a number of TMRs received exceeds a certain threshold value. The method includes detecting a TMR generating a command to stop a channel from receiving non-data frames while continuing to receive data frames from a Fibre Channel interface; and generating an interrupt to a processor after a certain number of TMRs are received.

Abstract: A write validation system that includes a first address signature collector module that generates a first address signature that is indicative of a write address of data when the data is received at a memory control module. A second address signature collector module generates a second address signature that is indicative of the write address of the data when the data is transferred from the memory control module. An address signature validation module receives the first address signature from the first address signature collector module, receives the second address signature from the second address signature collector module, and compares the first address signature to the second address signature.

Abstract: Method and system for transferring data between a computing system and a storage device is provided. The system includes a storage controller including a frame snooper module that detects a TMR and generates a pause signal to a channel that stops the channel from sending any non-data frames to a buffer memory, wherein the channel continues to receive and process data frames while the channel is stopped from sending the command frames to the buffer memory; a counter for counting TMRs; and logic for generating an interrupt if a number of TMRs received exceeds a certain threshold value. The method includes detecting a TMR generating a command to stop a channel from receiving non-data frames while continuing to receive data frames from a Fiber Channel interface; and generating an interrupt to a processor after a certain number of TMRs are received.

Abstract: A system and method for dynamically writing to and reading from an internal register space of a chip using a TAP controller without interfering with the normal operation of the chip is provided. Data that is to be written is loaded into a data register in the TAP controller before being written in the internal register space and the write instructions are loaded into an instruction register of the TAP controller. The address of the internal register space from where data is to be read is also loaded to the data register. Data is read and/or written from the internal register space after the TAP controller gets access to the internal register space via arbitration.

Abstract: A method and system using a storage controller for transferring data between a storage device and a host system is provided. The storage controller includes, a power save module that is enabled in a power save mode after a receive logic in the storage controller has processed all frames and during the power save mode at least a clock is turned off to save power while a clock for operating the receive logic is kept on to process any unsolicited frames that may be received by the receive logic. The storage controller operates in a single frame mode during the power save mode to process any unsolicited frames. Setting a bit in a configuration register for a processor enables the power save mode. The power save mode is enabled after a memory controller is in a self-refresh mode.

Abstract: A storage controller includes a first memory that stores a plurality of data blocks that include first and second noncontiguous data segments. A queue module stores data lengths and data start addresses of the first and second data segments. A read assembly module communicates with the first memory and the queue module, receives a request to read the first and second data segments from a host, reads the plurality of data blocks from the first memory, extracts the first and second data segments from the read plurality of data blocks based on the data lengths and data start addresses after the plurality of data blocks is read from the first memory, and transfers the first and second data segments contiguously to the host.

Abstract: A history module for monitoring plural components in an embedded disk controller with a first main processor operationally coupled to a first bus and a second processor operationally coupled to a second bus is provided. The history module includes an event control module that receives break point conditions that stops the history module from recording information of a component; and a first register that allows selection or-de-selection of certain components in the embedded disk controller. The first register can also store a trigger mode value, which specifies a number of entries that are made in history module buffer(s) after a break point condition is detected.

Abstract: A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.

Abstract: A history module for monitoring plural components in an embedded disk controller with a first main processor operationally coupled to a first bus and a second processor operationally coupled to a second bus is provided. The history module includes an event control module that receives break point conditions that stops the history module from recording information of a component; and a first register that allows selection or-de-selection of certain components in the embedded disk controller. The first register can also store a trigger mode value, which specifies a number of entries that are made in history module buffer(s) after a break point condition is detected.

Abstract: In a controller integrated circuit, which controls the operation of a peripheral storage device, a transfer monitoring circuit that facilitates the monitoring of successful transfers from outside the controller integrated circuit. The circuit includes a counter circuit that counts the number of successful transfers, a value storing register, a comparison circuit to compare the counter value to the value stored in the register and generate a result. The transfer monitoring circuit speeds up the operation of the controller integrated circuit especially during recovery from error conditions. The monitoring circuit also allows for a more optimal use of a look-ahead cache.

Abstract: In a controller integrated circuit, which controls the operation of a peripheral storage device, a transfer monitoring circuit that facilitates the monitoring of successful transfers from outside the controller integrated circuit. The circuit includes a counter circuit that counts the number of successful transfers, a value storing register, a comparison circuit to compare the counter value to the value stored in the register and generate a result. The transfer monitoring circuit speeds up the operation of the controller integrated circuit especially during recovery from error conditions. The monitoring circuit also allows for a more optimal use of a look-ahead cache.