Abstract: Embodiments described herein provide a mechanism to use an on-chip buffer memory in conjunction with an off-chip buffer memory for interim NAND write data storage. Specifically, the program data flows through the on-chip buffer memory to the NAND memory, while simultaneously a copy of the NAND program data is buffered in one or more circular buffer structures within the off-chip buffer memory.

Abstract: A system and method for verifying an identifier of a command. The method includes receiving an incoming command and sending a first alert to auto-logging hardware, wherein the auto-logging hardware sends a fetch instruction in response to receiving the first alert; retrieving an identifier of the incoming command in response to the fetch instruction and sending a second alert to the auto-logging hardware, wherein the auto-logging hardware sends a search instruction in response to receiving the second alert; and searching for the identifier of the incoming command in a table in response to the search instruction, the table storing identifiers previously assigned to other commands, wherein the incoming command is logged into the search table and marked as a searched command after the search for the first identifier in the table has completed successfully.

Abstract: Apparatus having corresponding methods and computer-readable media comprise: a memory having a plurality of ports; a plurality of processors, wherein each processor is configured to access a respective port of the memory, and wherein each processor is configured to wait responsive to assertion of a respective wait signal; and an arbiter configured to assert the wait signals responsive to memory enable signals asserted by the processors such that the memory is accessed by only one of the processors at a time.

Abstract: A controller and a method for interfacing between a host and storage medium. A storage medium interface includes CH0 circuitry for performing a CH0 process to access a buffer memory on behalf of the storage medium. A host interface includes CH1 circuitry for performing a CH1 process to access the buffer memory on behalf of the host. Access to the buffer memory is arbitrated in sequential tenures to each channel of the multi-channel bus within a maximum arbitration round trip time defined by the time taken by the storage medium to move a distance corresponding to N sectors in which N is greater than one. In the CH0 tenure, the CH0 process transfers data corresponding to N sectors of the storage medium in a multi-sector burst. The length of the tenure of the CH0 channel is pre-designated so that the multi-sector burst is completed within the CH0 tenure.

Abstract: A write validation system that includes a first address signature collector module that generates a first address signature that is indicative of a write address of data when the data is received at a memory control module. A second address signature collector module generates a second address signature that is indicative of the write address of the data when the data is transferred from the memory control module. An address signature validation module receives the first address signature from the first address signature collector module, receives the second address signature from the second address signature collector module, and compares the first address signature to the second address signature.