Abstract: A forward-looking proximity sensor comprises one or more antenna elements mounted on a carrier platform in a lateral direction of said carrier platform, said antenna elements being configured to transmit a modulated signal in a direction of travel of said carrier platform, said antenna elements receiving a reflected portion of said modulated signal from said target; and a processing unit configured to generate said modulated signal based on a baseband signal and a carrier signal, said processing unit further determining characteristics of said target based on said reflected portion of said modulated signal, said characteristics of said target indicating a range of said target and at least one feature of said target.

Abstract: A virtual tracer system and methods for operating the system to track a moving object are disclosed. The virtual tracer system may transmit a continuous waveform signal to a plurality of projectiles traveling in an outbound direction with respect to a carrier of the system. The virtual tracer system may further receive a signal reflected from the projectiles in response to the transmitted continuous waveform signal, and may determine a track of the projectiles based on the reflected signal.

Abstract: A forward-looking proximity sensor comprises one or more antenna elements mounted on a carrier platform in a lateral direction of said carrier platform, said antenna elements being configured to transmit a modulated signal in a direction of travel of said carrier platform, said antenna elements receiving a reflected portion of said modulated signal from said target; and a processing unit configured to generate said modulated signal based on a baseband signal and a carrier signal, said processing unit further determining characteristics of said target based on said reflected portion of said modulated signal, said characteristics of said target indicating a range of said target and at least one feature of said target.

Abstract: A bed foundation is provided by a rectangular panel having a flat upper face and downwardly depending side and end walls to form an open box-like structure. Downwardly facing mounting bores are provided at least at the corners of the foundation, and support legs are engaged in the bores to support the foundation at a spacing above a floor surface. The foundation is made entirely or substantially entirely from an expanded rigid plastic foam material with high flame retardancy. In an alternative, the side and end walls are eliminated and the legs are supported directly at the corners of a single flat panel, with springs tacked to the upper surface and surrounded by a suitable cover.

Abstract: A high-voltage bipolar transistor and fabrication method that comprises a shield electrode (or field-termination electrode) located between bond pads and underlying semiconductor material. The shield electrode is sandwiched between two isolating dielectric layers. High-voltage applied to the bond pad establishes an electric field between the bond pad and the shield electrode), preventing field penetration into and inversion of the underlying semiconductor material. Using this overlapping field-termination structure, low leakage current and high breakdown voltage is maintained in the transistor. The present overlapping field-termination structure provides an effective field termination underneath the bond pads, and because of its overlapping design, provides for a more compact transistor.

Abstract: A doping profile is disclosed for realizing a varactor diode that exhibits a high breakdown voltage V.sub.BR, e.g.,>100 volts, and a capacitance which has a bi-level characteristic. In particular, the capacitance has a C.sub.max level and a C.sub.min level. The doping profile includes two lightly doped regions and, between them, a third region with higher doping. The doping concentrations and widths of the first two regions substantially set the tuning ratio of C.sub.max /C.sub.min, and the doping concentration and width of the third region substantially sets the transition voltage V.sub.TR between the bi-level capacitances.

Abstract: A photoresist process combined with wet chemical etching and silicon oxide evaporation and self-aligned lift-off is used to reduce the parasitic (extrinsic) base-collector junction capacitance (C.sub.BC) of InP-based heterojunction bipolar transistors (HBTs). At least a portion of the mesa related to the base contact is etched around the intrinsic device area and then back-filled with evaporated oxide. The base contact pad is then formed over the back-filled oxide, thus reducing the extrinsic device area. This process provides a self-aligned etching of a mesa and deposition and lift-off of the back-fill oxide in one single photoresist processing step. The process is simple and reproducible and provides very high yield. It also eliminates the need for costly and complicated dry-etching techniques.