Abstract: A semiconductor structure comprising a polysilicon pad, a metal pad separated from the polysilicon pad by an insulator, and a metal via connecting the pads. A fuse is formed at the intersection of the polysilicon pad and via.

Abstract: A programmable read only memory (PROM) including an array of polysilicon fuse elements. The fuse array is formed within a semiconductor substrate including first and second patterned signal layers electrically insulated from one another. Each polysilicon fuse element within the array connects a first electrical conductor residing in the first patterned signal layer with a second electrical conductor residing in the second patterned signal layer. The polysilicon fuse element is in the form of a narrow strip and is folded in order to cause a current flowing through the clement to crowd, lowering the amount of current required to heat the fuse element to its melting point, i.e. the threshold current. The PROM is programmed by passing a threshold current through selected fuse elements.

Abstract: A typical Programmable Logic Array (PLA) provides an available logic function, or precursor, which a user modifies to obtain a desired logic function. For example, the precursor may be (A.multidot.A19 B.multidot.B+(A.multidot.A.multidot.B.multidot.B). The user obtains the desired function, such as (A.multidot.)+(A.multidot.B), by blowing fuses inside the PLA. The fuse-blowing physically blocks data signals (such as the deleted and the deleted B in the first term) from reaching an internal AND gate which performs the ".multidot." operation. However, this fuse-blowing is permanent, and irreversible. In contrast, one form of the invention does the blocking by using a NAND gate. That is, the data signal, such as the "B," is applied to one input of the NAND gate. A capacitor is connected to the other input. The user stores either a ONE or a ZERO on the capacitor. A ONE blocks the data signal (the output of the NAND cannot change). A ZERO passes the data signal (the output is the inverse of the data signal).

Abstract: A semiconductor structure comprising a polysilicon pad, a metal pad separated from the polysilicon pad by an insulator, and a metal via connecting the pads. A fuse is formed at the intersection of the polysilicon pad and via.

Abstract: An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.

Abstract: An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.

Abstract: A process for fabricating aligned, stacked CMOS devices. Following the formation of the lower FET device, conformal undoped and doped oxide layers are formed thereover so that the level of the upper surface of the common gate electrode is above the doped oxide as formed in the source and drain regions of the lower FET device. A planarizing photoresist is then deposited and etched in conjunction with the oxide to the upper surface of the gate electrode. The exposed gate electrode is covered with a gate oxide layer, and a polycrystalline silicon layer for recrystallization to an upper FET device. Updiffusion from the residuals of doped oxide then creates an upper FET device with source and drain regions aligned to the gate oxide thereof and the underlying common gate electrode.