Abstract: Computer computation of correctly rounded floating point summation is described. An example of apparatus includes a first circuit to sort multiple floating point (FP) values based on an exponent of each FP value and store the sorted FP values in a buffer, and to provide the plurality of FP values for summation sequentially in a sorted order starting with a FP value having a smallest exponent; a second circuit to iteratively sum the FP values and store an accumulated value, generate and store a residual value representing fully resolved bits from the accumulator, and generate an intermediate output including the residual value; and a third circuit to perform final rounding of the output, the final rounded output being a correctly rounded summation of the maximum floating point values.

Abstract: Computer computation of exact floating point addition is described. An example of an apparatus includes a first circuit to add first and second floating point inputs, including sorting the inputs to identify a larger input and a smaller input, adding bits in an upper portion of the smaller input to bits of the larger input, generating a high intermediate value based on the sum, and a generating a low intermediate value based on a lower portion of the lower input; and a second circuit to generate first and second outputs based on the high and low intermediate values, wherein the first output plus the second output exactly equals the first input plus the second input.

Abstract: Described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. The constant modulo operation calculates a result for array of bits xi, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). Circuitry to perform such operation can be configured to compress the array of bits xi, width n into an array of bits yi width m. The techniques described herein enable the design of optimal circuitry via iterative exploration of all potential reduction strategies that are available given the input constraints.

Abstract: The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.

Abstract: An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.

Abstract: Described herein is a computer memory system comprising a plurality of memory banks or other memory structures and circuitry configured to implement a hash function that produces output values that evenly distribute strided memory accesses across the plurality of memory structures. The memory banks can be cache memory banks that may include a plurality of cache lines, cache sets, or cache ways. The memory banks can also be DRAM memory banks accessed through different memory channels. The hash function facilitates the even distribution across memory structures in the face of a plurality of different strided memory access patterns.

Abstract: Spaced apart single entries are driven into a mineral deposit to be developed by means of a short wall mining machine. A specially designed concrete-receiving slip-form located in the center of the entry is pulled along by a battery of roof supports which are advanced in line behind the mining machine. Quick setting concrete pumped into the anchored slip-form sets up into a wall isolating the two sides of the entry. The slip-form is then released for each successive mining run.