Patents by Inventor Willibrordus Gerardus Maria van den Hoek
Willibrordus Gerardus Maria van den Hoek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113092Abstract: A light emitting device includes a backplane, an array of light emitting diodes attached to a frontside of the backplane, a positive tone, imageable dielectric material layer, such as a positive photoresist layer, located on the frontside of the backplane and laterally surrounding the array of light emitting diodes, such that sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile, and at least one common conductive layer located over the positive tone, imageable dielectric material layer and contacting the light emitting diodes.Type: ApplicationFiled: October 9, 2023Publication date: April 4, 2024Inventors: Willibrordus Gerardus Maria VAN DEN HOEK, Tsun Yin LAU, Cameron DANESH, Fariba DANESH
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Patent number: 11784176Abstract: A light emitting device includes a backplane, an array of light emitting diodes attached to a frontside of the backplane, a positive tone, imageable dielectric material layer, such as a positive photoresist layer, located on the frontside of the backplane and laterally surrounding the array of light emitting diodes, such that sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile, and at least one common conductive layer located over the positive tone, imageable dielectric material layer and contacting the light emitting diodes.Type: GrantFiled: August 10, 2022Date of Patent: October 10, 2023Assignee: NANOSYS, INC.Inventors: Willibrordus Gerardus Maria Van Den Hoek, Tsun Yin Lau, Cameron Danesh, Fariba Danesh
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Publication number: 20220384404Abstract: A light emitting device includes a backplane, an array of light emitting diodes attached to a frontside of the backplane, a positive tone, imageable dielectric material layer, such as a positive photoresist layer, located on the frontside of the backplane and laterally surrounding the array of light emitting diodes, such that sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile, and at least one common conductive layer located over the positive tone, imageable dielectric material layer and contacting the light emitting diodes.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Willibrordus Gerardus Maria VAN DEN HOEK, Tsun Yin LAU, Cameron DANESH, Fariba DANESH
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Patent number: 11444065Abstract: A light emitting device includes a backplane, an array of light emitting diodes attached to a frontside of the backplane, a positive tone, imageable dielectric material layer, such as a positive photoresist layer, located on the frontside of the backplane and laterally surrounding the array of light emitting diodes, such that sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile, and at least one common conductive layer located over the positive tone, imageable dielectric material layer and contacting the light emitting diodes.Type: GrantFiled: May 27, 2020Date of Patent: September 13, 2022Assignee: NANOSYS, INC.Inventors: Willibrordus Gerardus Maria Van Den Hoek, Tsun Yin Lau, Cameron Danesh, Fariba Danesh
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Publication number: 20220013446Abstract: A metallized via structure may comprise a via hole, a barrier layer deposited within the via hole, and a metallic plug disposed within the via hole. The via hole may be formed in a device package, and the via hole may be defined by at least one interior wall of the device package. The barrier layer may be disposed upon the at least one interior wall to form a barrier layer lined via hole. The metallic plug may be disposed within the barrier lined via hole by pressurized injection of a molten metal, such that the barrier layer is situated between the metallic plug and the at least one interior wall. The barrier layer may be situated to prevent the metallic plug from contacting the interior wall.Type: ApplicationFiled: July 7, 2020Publication date: January 13, 2022Inventors: Jeff S. Baloun, Willibrordus Gerardus Maria van den Hoek
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Patent number: 10879079Abstract: The invention is directed to a method for treating an electronic device that is encapsulated in a plastic package, said method comprising the steps of providing a gas stream comprising a hydrogen source; inducing a hydrogen-containing plasma stream from said gas; and directing the hydrogen-containing plasma stream to the plastic package to etch the plastic package.Type: GrantFiled: July 20, 2017Date of Patent: December 29, 2020Assignee: JIACO Instruments Holding B.V.Inventors: Jiaqi Tang, Cornelis Ignatius Maria Beenakker, Willibrordus Gerardus Maria Van Den Hoek
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Publication number: 20200381411Abstract: A light emitting device includes a backplane, an array of light emitting diodes attached to a frontside of the backplane, a positive tone, imageable dielectric material layer, such as a positive photoresist layer, located on the frontside of the backplane and laterally surrounding the array of light emitting diodes, such that sidewalls of the light emitting diodes contacting the positive tone, imageable dielectric material layer have a respective reentrant vertical cross-sectional profile, and at least one common conductive layer located over the positive tone, imageable dielectric material layer and contacting the light emitting diodes.Type: ApplicationFiled: May 27, 2020Publication date: December 3, 2020Inventors: Willibrordus Gerardus Maria VAN DEN HOEK, Tsun Yin LAU, Cameron DANESH, Fariba DANESH
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Publication number: 20200279749Abstract: The invention is directed to a method for treating an electronic device that is encapsulated in a plastic package, said method comprising the steps of providing a gas stream comprising a hydrogen source; inducing a hydrogen-containing plasma stream from said gas; and directing the hydrogen-containing plasma stream to the plastic package to etch the plastic package.Type: ApplicationFiled: July 20, 2017Publication date: September 3, 2020Applicant: JIACO Instruments Holding B.V.Inventors: Jiaqi Tang, Cornelis Ignatius Maria Beenakker, Willibrordus Gerardus Maria Van Den Hoek
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Patent number: 10204803Abstract: A semiconductor device and method of making the semiconductor device is described. A semiconductor die can be provided. A polymer layer can be formed over the semiconductor die. A via can be formed in the polymer layer. The polymer layer can be cross-linked in a first process, after forming the via, by exposing the polymer layer to ultraviolet (UV) radiation to form a sidewall of the via with via sidewall slope greater than or equal to 45 degrees and to further form a cross-linked via sidewall surface. The polymer layer can be thermally cured in a second process after the first process, wherein a maximum ramp-up rate from room temperature to a peak temperature of the second process is greater than 10 degrees Celsius per minute.Type: GrantFiled: October 6, 2015Date of Patent: February 12, 2019Assignee: Deca Technologies Inc.Inventors: William Boyd Rogers, Willibrordus Gerardus Maria van den Hoek
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Publication number: 20160027666Abstract: A semiconductor device and method of making the semiconductor device is described. A semiconductor die can be provided. A polymer layer can be formed over the semiconductor die. A via can be formed in the polymer layer. The polymer layer can be cross-linked in a first process, after forming the via, by exposing the polymer layer to ultraviolet (UV) radiation to form a sidewall of the via with via sidewall slope greater than or equal to 45 degrees and to further form a cross-linked via sidewall surface. The polymer layer can be thermally cured in a second process after the first process, wherein a maximum ramp-up rate from room temperature to a peak temperature of the second process is greater than 10 degrees Celsius per minute.Type: ApplicationFiled: October 6, 2015Publication date: January 28, 2016Inventors: William Boyd Rogers, Willibrordus Gerardus Maria van den Hoek
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Patent number: 9159547Abstract: A semiconductor device and method of making the semiconductor device is described. A semiconductor die is provided. A polymer layer is formed over the semiconductor die. A via is formed in the polymer layer. The polymer layer is crosslinked in a first process. The polymer layer is thermally cured in a second process. The polymer layer can comprise polybenzoxazoles (PBO), polyimide, benzocyclobutene (BCB), or siloxane-based polymers. A surface of the polymer layer can be crosslinked by a UV bake to control a slope of the via during subsequent curing. The second process can further comprise thermally curing the polymer layer using conduction, convection, infrared, or microwave heating. The polymer layer can be thermally cured by increasing a temperature of the polymer at a rate greater than or equal to 10 degrees Celsius per minute, and can be completely cured in less than or equal to 60 minutes.Type: GrantFiled: September 17, 2013Date of Patent: October 13, 2015Assignee: DECA Technologies Inc.Inventors: William Boyd Rogers, Willibrordus Gerardus Maria van den Hoek
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Patent number: 9088020Abstract: A removable, or reusable, template suitable for forming three dimensional structures of various devices ranging from photovoltaics to electrodes for electrochemical cells is disclosed.Type: GrantFiled: December 7, 2012Date of Patent: July 21, 2015Assignee: Integrated Photovoltaics, Inc.Inventors: Sharone Zehavi, Willibrordus Gerardus Maria van den Hoek
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Publication number: 20150079805Abstract: A semiconductor device and method of making the semiconductor device is described. A semiconductor die is provided. A polymer layer is formed over the semiconductor die. A via is formed in the polymer layer. The polymer layer is crosslinked in a first process. The polymer layer is thermally cured in a second process. The polymer layer can comprise polybenzoxazoles (PBO), polyimide, benzocyclobutene (BCB), or siloxane-based polymers. A surface of the polymer layer can be crosslinked by a UV bake to control a slope of the via during subsequent curing. The second process can further comprise thermally curing the polymer layer using conduction, convection, infrared, or microwave heating. The polymer layer can be thermally cured by increasing a temperature of the polymer at a rate greater than or equal to 10 degrees Celsius per minute, and can be completely cured in less than or equal to 60 minutes.Type: ApplicationFiled: September 17, 2013Publication date: March 19, 2015Applicant: DECA TECHNOLOGIES INC.Inventors: William Boyd Rogers, Willibrordus Gerardus Maria van den Hoek
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Patent number: 7972976Abstract: Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.Type: GrantFiled: October 27, 2009Date of Patent: July 5, 2011Assignee: Novellus Systems, Inc.Inventors: Willibrordus Gerardus Maria van den Hoek, Nerissa S. Draeger, Raashina Humayun, Richard S. Hill, Jianing Sun, Gary William Ray
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Patent number: 7629224Abstract: Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.Type: GrantFiled: November 28, 2006Date of Patent: December 8, 2009Assignee: Novellus Systems, Inc.Inventors: Willibrordus Gerardus Maria van den Hoek, Nerissa S. Draeger, Raashina Humayun, Richard S. Hill, Jianing Sun, Gary Ray
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Patent number: 7456101Abstract: Methods for depositing a ruthenium metal layer on a dielectric substrate are provided. The methods involve, for instance, exposing the dielectric substrate to an amine-containing compound, followed by exposing the substrate to a ruthenium precursor and an optional co-reactant such that the amine-containing compound facilitates the nucleation on the dielectric surface.Type: GrantFiled: March 13, 2007Date of Patent: November 25, 2008Assignee: Novellus Systems, Inc.Inventors: Sanjay Gopinath, Jeremie Dalton, Jason M. Blackburn, John Drewery, Willibrordus Gerardus Maria van den Hoek
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Patent number: 7211509Abstract: Methods for depositing a ruthenium metal layer on a dielectric substrate are provided. The methods involve, for instance, exposing the dielectric substrate to an amine-containing compound, followed by exposing the substrate to a ruthenium precursor and an optional co-reactant such that the amine-containing compound facilitates the nucleation on the dielectric surface.Type: GrantFiled: June 14, 2004Date of Patent: May 1, 2007Assignee: Novellus Systems, Inc,Inventors: Sanjay Gopinath, Jeremie Dalton, Jason M. Blackburn, John Drewery, Willibrordus Gerardus Maria van den Hoek
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Patent number: 7166531Abstract: Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.Type: GrantFiled: January 31, 2005Date of Patent: January 23, 2007Assignee: Novellus Systems, Inc.Inventors: Willibrordus Gerardus Maria van den Hoek, Nerissa S. Draeger, Raashina Humayun, Richard S. Hill, Jianing Sun, Gary William Ray
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Patent number: 6995439Abstract: Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a pre-formed layer of semiconductor to produce a porous semiconductor layer.Type: GrantFiled: March 17, 2004Date of Patent: February 7, 2006Assignee: Novellus Systems, Inc.Inventors: Richard S. Hill, Willibrordus Gerardus Maria van den Hoek, Robert H. Havemann
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Patent number: 6753250Abstract: Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a preformed layer of semiconductor to produce a porous semiconductor layer.Type: GrantFiled: June 12, 2002Date of Patent: June 22, 2004Assignee: Novellus Systems, Inc.Inventors: Richard S. Hill, Willibrordus Gerardus Maria van den Hoek, Robert H. Havemann