Abstract: An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.

Abstract: An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.