Patents by Inventor Wilson E. Smith

Wilson E. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240151895
    Abstract: A variety of illumination devices are disclosed that are configured to manipulate light provided by one or more light-emitting elements (LEEs). In general, embodiments of the illumination devices feature one or more optical couplers that redirect illumination from the LEEs to a reflector which then directs the light into a range of angles. In some embodiments, the illumination device includes a second reflector that reflects at least some of the light from the first reflector. In certain embodiments, the illumination device includes a light guide that guides light from the collector to the first reflector. The components of the illumination device can be configured to provide illumination devices that can provide a variety of intensity distributions. Such illumination devices can be configured to provide light for particular lighting applications, including office lighting, task lighting, cabinet lighting, garage lighting, wall wash, stack lighting, and downlighting.
    Type: Application
    Filed: June 2, 2023
    Publication date: May 9, 2024
    Inventors: Wilson Dau, Robert C. Gardner, George Lerman, Louis Lerman, Christopher H. Lowery, Brian D. Ogonowsky, George E. Smith, Ingo Speier, Robert V. Steele, Jacqueline Teng, Allan Brent York, Hans Peter Stormberg
  • Patent number: 10180866
    Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: January 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffrey J. Van Heuklon
  • Patent number: 9389937
    Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: July 12, 2016
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Jerry D. Ackaret, Sumeet Kochar, Randolph S. Kolvick, Wilson E. Smith
  • Patent number: 9081676
    Abstract: Operating computer memory in a computer including dynamically monitoring, by a predictive failure analysis (‘PFA’) module, correctable memory errors and memory temperature and managing cooling resources in the computer in dependence upon the correctable memory errors and memory temperature.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: July 14, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Jerry D. Ackaret, Robert M. Dunn, Anna H. Siskind, Wilson E. Smith
  • Publication number: 20150186230
    Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.
    Type: Application
    Filed: February 23, 2015
    Publication date: July 2, 2015
    Inventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffrey J. Van Heuklon
  • Publication number: 20150143054
    Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Inventors: Jerry D. Ackaret, Sumeet Kochar, Randolph S. Kolvick, Wilson E. Smith
  • Publication number: 20150143052
    Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: International Business Machines Corporation
    Inventors: JERRY D. ACKARET, SUMEET KOCHAR, RANDOLPH S. KOLVICK, WILSON E. SMITH
  • Patent number: 9003223
    Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffery J. Van Heuklon
  • Publication number: 20140089725
    Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffery J. Van Heuklon
  • Patent number: 8635488
    Abstract: A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jerry D. Ackaret, Justin P. Bandholz, Brian E. Bigelow, Joseph E. Bolan, Kevin M. Cash, David L. Cowell, Martin J. Crippen, Christopher L. Durham, Jeffery M. Franke, James E. Hughes, David J. Jensen, John K. Langgood, Bay Van Nguyen, James A. O'Connor, Derek Robertson, John M. Sheplock, Wilson E. Smith
  • Publication number: 20130117601
    Abstract: A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 9, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jerry D. Ackaret, Justin P. Bandholz, Brian E. Bigelow, Joseph E. Bolan, Kevin M. Cash, David L. Cowell, Martin J. Crippen, Christopher L. Durham, Jeffery M. Franke, James E. Hughes, David J. Jensen, John K. Langgood, Bay Van Nguyen, James A. O'Connor, Derek Robertson, John M. Sheplock, Wilson E. Smith
  • Publication number: 20100306598
    Abstract: Operating computer memory in a computer including dynamically monitoring, by a predictive failure analysis (‘PFA’) module, correctable memory errors and memory temperature and managing cooling resources in the computer in dependence upon the correctable memory errors and memory temperature.
    Type: Application
    Filed: June 2, 2009
    Publication date: December 2, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jerry D. Ackaret, Robert M. Dunn, Anna H. Siskind, Wilson E. Smith
  • Patent number: 5036514
    Abstract: A method for correcting error weights in a communication system in which at least one error condition can result from more than one cause. Stations on the system send error reports to an error monitor station which maintains a count of the number of stations reporting an error having multiple causes and periodically corrects the error weights assigned to each station as a function of the maximum number of errors reported by any station only when the number of stations reporting a multiple cause error exceeds a predetermined value.
    Type: Grant
    Filed: November 9, 1989
    Date of Patent: July 30, 1991
    Assignee: International Business Machines Corp.
    Inventors: Robert W. Downes, Wilson E. Smith, Ronald E. Suciu, Kenneth T. Wilson
  • Patent number: 4769761
    Abstract: Stations of a communications network maintain a set of counters which measure the frequency of occurrence of soft errors in said network. Periodically, each station generates and transmits an error report containing the error counts to a ring error monitor provided in one of the stations. The ring error monitor analyzes the report and calculates and stores weighted error counts for stations in an error domain. The stored error counts are integrated, over a selected time interval, and compared with a threshold value normal for a communications network, operating at acceptable error rate. The results of the comparison set error flags if the limits are exceeded indicating possible future station failures.
    Type: Grant
    Filed: October 9, 1986
    Date of Patent: September 6, 1988
    Assignee: International Business Machines Corporation
    Inventors: Robert W. Downes, Wilson E. Smith