Patents by Inventor Wilson E. Smith
Wilson E. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240151895Abstract: A variety of illumination devices are disclosed that are configured to manipulate light provided by one or more light-emitting elements (LEEs). In general, embodiments of the illumination devices feature one or more optical couplers that redirect illumination from the LEEs to a reflector which then directs the light into a range of angles. In some embodiments, the illumination device includes a second reflector that reflects at least some of the light from the first reflector. In certain embodiments, the illumination device includes a light guide that guides light from the collector to the first reflector. The components of the illumination device can be configured to provide illumination devices that can provide a variety of intensity distributions. Such illumination devices can be configured to provide light for particular lighting applications, including office lighting, task lighting, cabinet lighting, garage lighting, wall wash, stack lighting, and downlighting.Type: ApplicationFiled: June 2, 2023Publication date: May 9, 2024Inventors: Wilson Dau, Robert C. Gardner, George Lerman, Louis Lerman, Christopher H. Lowery, Brian D. Ogonowsky, George E. Smith, Ingo Speier, Robert V. Steele, Jacqueline Teng, Allan Brent York, Hans Peter Stormberg
-
Patent number: 10180866Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.Type: GrantFiled: February 23, 2015Date of Patent: January 15, 2019Assignee: International Business Machines CorporationInventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffrey J. Van Heuklon
-
Patent number: 9389937Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.Type: GrantFiled: November 19, 2013Date of Patent: July 12, 2016Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Jerry D. Ackaret, Sumeet Kochar, Randolph S. Kolvick, Wilson E. Smith
-
Patent number: 9081676Abstract: Operating computer memory in a computer including dynamically monitoring, by a predictive failure analysis (‘PFA’) module, correctable memory errors and memory temperature and managing cooling resources in the computer in dependence upon the correctable memory errors and memory temperature.Type: GrantFiled: June 2, 2009Date of Patent: July 14, 2015Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Jerry D. Ackaret, Robert M. Dunn, Anna H. Siskind, Wilson E. Smith
-
Publication number: 20150186230Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.Type: ApplicationFiled: February 23, 2015Publication date: July 2, 2015Inventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffrey J. Van Heuklon
-
Publication number: 20150143054Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Inventors: Jerry D. Ackaret, Sumeet Kochar, Randolph S. Kolvick, Wilson E. Smith
-
Publication number: 20150143052Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.Type: ApplicationFiled: November 19, 2013Publication date: May 21, 2015Applicant: International Business Machines CorporationInventors: JERRY D. ACKARET, SUMEET KOCHAR, RANDOLPH S. KOLVICK, WILSON E. SMITH
-
Patent number: 9003223Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.Type: GrantFiled: September 27, 2012Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffery J. Van Heuklon
-
Publication number: 20140089725Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.Type: ApplicationFiled: September 27, 2012Publication date: March 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffery J. Van Heuklon
-
Patent number: 8635488Abstract: A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.Type: GrantFiled: November 8, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Jerry D. Ackaret, Justin P. Bandholz, Brian E. Bigelow, Joseph E. Bolan, Kevin M. Cash, David L. Cowell, Martin J. Crippen, Christopher L. Durham, Jeffery M. Franke, James E. Hughes, David J. Jensen, John K. Langgood, Bay Van Nguyen, James A. O'Connor, Derek Robertson, John M. Sheplock, Wilson E. Smith
-
Publication number: 20130117601Abstract: A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.Type: ApplicationFiled: November 8, 2011Publication date: May 9, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jerry D. Ackaret, Justin P. Bandholz, Brian E. Bigelow, Joseph E. Bolan, Kevin M. Cash, David L. Cowell, Martin J. Crippen, Christopher L. Durham, Jeffery M. Franke, James E. Hughes, David J. Jensen, John K. Langgood, Bay Van Nguyen, James A. O'Connor, Derek Robertson, John M. Sheplock, Wilson E. Smith
-
Publication number: 20100306598Abstract: Operating computer memory in a computer including dynamically monitoring, by a predictive failure analysis (‘PFA’) module, correctable memory errors and memory temperature and managing cooling resources in the computer in dependence upon the correctable memory errors and memory temperature.Type: ApplicationFiled: June 2, 2009Publication date: December 2, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jerry D. Ackaret, Robert M. Dunn, Anna H. Siskind, Wilson E. Smith
-
Patent number: 5036514Abstract: A method for correcting error weights in a communication system in which at least one error condition can result from more than one cause. Stations on the system send error reports to an error monitor station which maintains a count of the number of stations reporting an error having multiple causes and periodically corrects the error weights assigned to each station as a function of the maximum number of errors reported by any station only when the number of stations reporting a multiple cause error exceeds a predetermined value.Type: GrantFiled: November 9, 1989Date of Patent: July 30, 1991Assignee: International Business Machines Corp.Inventors: Robert W. Downes, Wilson E. Smith, Ronald E. Suciu, Kenneth T. Wilson
-
Patent number: 4769761Abstract: Stations of a communications network maintain a set of counters which measure the frequency of occurrence of soft errors in said network. Periodically, each station generates and transmits an error report containing the error counts to a ring error monitor provided in one of the stations. The ring error monitor analyzes the report and calculates and stores weighted error counts for stations in an error domain. The stored error counts are integrated, over a selected time interval, and compared with a threshold value normal for a communications network, operating at acceptable error rate. The results of the comparison set error flags if the limits are exceeded indicating possible future station failures.Type: GrantFiled: October 9, 1986Date of Patent: September 6, 1988Assignee: International Business Machines CorporationInventors: Robert W. Downes, Wilson E. Smith