Patents by Inventor Wilson P. Snyder
Wilson P. Snyder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170255566Abstract: An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Inventors: Anna Kujtkowski, Wilson P. Snyder, II
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Publication number: 20170206171Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.Type: ApplicationFiled: March 31, 2017Publication date: July 20, 2017Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
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Patent number: 9703722Abstract: An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.Type: GrantFiled: November 13, 2015Date of Patent: July 11, 2017Assignee: CAVIUM, INC.Inventors: Anna Kujtkowski, Wilson P. Snyder, II
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Patent number: 9680742Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: June 13, 2017Assignee: Cavium, Inc.Inventors: Joseph B. Tompkins, Brian Robert Folsom, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins, Krupa Sagar O. S. Mylavarapu, Mahesh Dorai, Nagaraj G. Shirali, Ranjith Kumar V. Hallur
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Patent number: 9678717Abstract: In an embodiment, a method include, in a hardware processor, producing, by a block of hardware logic resources, a constrained randomly generated or pseudo-randomly generated number (CRGN) based on a bit mask stored in a register memory.Type: GrantFiled: November 13, 2015Date of Patent: June 13, 2017Assignee: CAVIUM, INC.Inventors: Wilson P. Snyder, II, Varada Ogale, Anna Kujtkowski, Albert Ma
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Patent number: 9645941Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.Type: GrantFiled: September 26, 2013Date of Patent: May 9, 2017Assignee: CAVIUM, INC.Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
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Patent number: 9639476Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache.Type: GrantFiled: September 26, 2013Date of Patent: May 2, 2017Assignee: CAVIUM, INC.Inventors: Bryan W. Chin, Shubhendu S. Mukherjee, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler
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Patent number: 9569362Abstract: An input/output bridge controls access to a memory by a number of devices. The bridge enforces ordering of access requests according to a register storing an order configuration, which can be programmed to accommodate a given application. When suspending an access request as a result of enforcing an order configuration, the bridge may also cause a prefetch at the memory for the suspended access request. Subsequently, following the completion of a previous access request meeting the order configuration, the suspended access request is released. Due to the prefetch, an access operation can be completed with minimal delay.Type: GrantFiled: November 13, 2014Date of Patent: February 14, 2017Assignee: Cavium, Inc.Inventors: Robert A. Sanzone, Wilson P. Snyder, II, Richard E. Kessler
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Patent number: 9559982Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: January 31, 2017Assignee: Cavium, Inc.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
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Patent number: 9529532Abstract: According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the one or more FPA coprocessors, a memory allocator (MA) hardware component allocates a free buffer, associated with a chip device of the multiple chip devices, to data associated with a work item. According to at least one aspect, the data associated with the work item represents a data packet.Type: GrantFiled: March 7, 2014Date of Patent: December 27, 2016Assignee: Cavium, Inc.Inventors: Richard E. Kessler, Wilson P. Snyder, II
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Patent number: 9529640Abstract: A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit (ODU) that provides a table having several entries, each entry storing a respective work queue entry, and a number of lists. Each of the lists may be associated with a respective processor configured to execute the work, and includes pointers to entries in the table. pointer is added to the list based on an indication of whether the associated processor accepts the WQE corresponding to the pointer.Type: GrantFiled: March 27, 2015Date of Patent: December 27, 2016Assignee: Cavium, Inc.Inventors: David Kravitz, Daniel E. Dever, Wilson P. Snyder, II
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Publication number: 20160314018Abstract: According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to a another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices.Type: ApplicationFiled: July 1, 2016Publication date: October 27, 2016Inventors: Richard E. Kessler, Wilson P. Snyder, II
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Patent number: 9431105Abstract: In an embodiment, a method for managing access to memory includes receiving requests for access to a memory from one or more devices, each particular request associated with one of a plurality of virtual channels. A tag is assigned to each request received. Each tag assigned is added to a linked list associated with the corresponding virtual channel. Each request received with the assigned tag is transmitted to the memory. Responses to the requests are received from the memory, each response having an associated tag, and the responses received are sent to the one or more devices based on the corresponding linked list and the corresponding tag.Type: GrantFiled: February 26, 2014Date of Patent: August 30, 2016Assignee: Cavium, Inc.Inventors: Robert A. Sanzone, Wilson P. Snyder, II
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Patent number: 9411644Abstract: According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to a another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices.Type: GrantFiled: March 7, 2014Date of Patent: August 9, 2016Assignee: Cavium, Inc.Inventors: Richard E. Kessler, Wilson P. Snyder, II
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Patent number: 9397938Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.Type: GrantFiled: February 28, 2014Date of Patent: July 19, 2016Assignee: Cavium, Inc.Inventors: Brian Robert Folsom, Joseph B. Tompkins, Wilson P. Snyder, II, Richard E. Kessler, Edwin Langevin, Andrew J. Jones, Ethan F. Robbins
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Patent number: 9390023Abstract: According to at least one example embodiment, a method and corresponding apparatus for conditionally storing data include initiating an atomic sequence by executing, by a core processor, an instruction/operation designed to initiate an atomic sequence. Executing the instruction designed to initiate the atomic sequence includes loading content associated with a memory location into a first cache memory, and maintaining an indication of the memory location and a copy of the corresponding content loaded. A conditional storing operation is then performed, the conditional storing operation includes a compare-and-swap operation, executed by a controller associated with a second cache memory, based on the maintained copy of the content and the indication of the memory location.Type: GrantFiled: October 3, 2013Date of Patent: July 12, 2016Assignee: Cavium, Inc.Inventors: Richard E. Kessler, David H. Asher, Michael Sean Bertone, Shubhendu S. Mukherjee, Wilson P. Snyder, II, John M. Perveiler, Christopher J. Comis
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Patent number: 9372800Abstract: A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory associated with one of the multiple chip devices. The first chip device receives a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices, and, in response, executes a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received.Type: GrantFiled: March 7, 2014Date of Patent: June 21, 2016Assignee: Cavium, Inc.Inventors: Isam Akkawi, Richard E. Kessler, David H. Asher, Bryan W. Chin, Wilson P. Snyder, II
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Publication number: 20160139806Abstract: An input/output bridge controls access to a memory by a number of devices and maintains an order of access requests under virtualization. In particular, the bridge manages and enforces order among multiple independent threads of requests to a memory. The bridge populates a number of ordered lists with received access requests based on a corresponding identifier of each access request. A top list is also maintained, where the top list is populated with access requests and a corresponding translated physical address. The bridge forwards access requests from the top list, maintaining the order of each of the independent threads.Type: ApplicationFiled: November 13, 2014Publication date: May 19, 2016Inventors: Robert A. Sanzone, Wilson P. Snyder, II, Richard E. Kessler
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Publication number: 20160139883Abstract: In an embodiment, a method include, in a hardware processor, producing, by a block of hardware logic resources, a constrained randomly generated or pseudo-randomly generated number (CRGN) based on a bit mask stored in a register memory.Type: ApplicationFiled: November 13, 2015Publication date: May 19, 2016Inventors: Wilson P. Snyder, II, Varada Ogale, Anna Kujtkowski, Albert Ma
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Publication number: 20160140050Abstract: An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.Type: ApplicationFiled: November 13, 2015Publication date: May 19, 2016Inventors: Anna Kujtkowski, Wilson P. Snyder, II