Abstract: A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller, implemented as a module or a single chip, to a target entity via either the network interface controller or the packet input processor is disclosed.

Abstract: A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller, implemented on a chip, to a target entity, is disclosed. Additionally, the system embodying a method for network switching of a data packet outgoing from an internal facing interface of a network interface controller portion of the network interface resource to a network is disclosed.

Abstract: A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet outgoing from an internal facing interface of a network interface controller portion of the network interface resource to a network is disclosed.

Abstract: A method and a system embodying the method for a multi-entity secure software transfer are disclosed, the method operating by: configuring a communication interface controller at each trusted hardware entity of a first hardware entity and a second hardware entity to disallow all external access except a communication link configuration access; establishing the communication link between the first hardware entity and the second hardware entity; configuring write access from the second hardware entity to only a first storage at the first hardware entity; and writing the secure software received from the second hardware entity via the communication link to the first storage at the first hardware entity.

Abstract: A new approach is proposed that contemplates systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can booted securely. Specifically, the network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. To this end, the network chip is configured to allow the BMC to access a plurality of registers of the network chip via an Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.

Abstract: A new approach is proposed that contemplates systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can be booted securely. The network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. The network chip is configured to allow the BMC to access a plurality of registers of the network chip via a Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.

Abstract: A method and system for flexibly assigning hardware resources to physical and virtual functions in a processor system supporting hardware virtualization is disclosed. The processor system includes a resource virtualization unit which is used to flexibly assign hardware resources to physical functions and also flexibly assign local functions to virtual functions associated with one or more of the physical functions. Thereby, standard PCI software is compatible with the physical functions and any associated virtualized hardware resources that have been flexibly assigned to the virtual and local functions.

Abstract: A method and a system embodying the method for data lockdown and data overlay in a packet to be transmitted, comprising providing a first and a second masks comprising one or more position(s) and a data value at each of the one or more position(s); aligning the masks with the packet; comparing the data value at each of the one or more position(s) in the first mask with the data value at the one or more aligned position(s) in the packet; optionally replacing a data value at each of the one or more position(s) in the packet with a data value at the one or more aligned position(s) in the second mask; and providing the packet for transmission if the data value at each of the one or more position(s) in the first mask and the data value at the one or more aligned position(s) in the packet agree.

Abstract: A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet.

Abstract: A method for parsing network packets via one or more clusters configured to parse network packets comprises receiving one or more packets to be parsed; determining a candidate cluster of the one or more clusters for parsing the one or more packets; transmitting the one or more packets to the candidate cluster; launching the candidate cluster to parse the one or more packets when a launch condition is met; and receiving parse results for the one or more packets from the candidate cluster. The launch condition may be met after transmitting the one or more packets meets a fraction of a parsing capacity of the candidate cluster. The fraction may be one such that the transmitting the one or more packets meets a parsing capacity of the candidate cluster. The launch condition may also be met when a time elapsed since a previous cluster was launched reaches a delay limit.

Abstract: A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller , implemented on a chip, to a target entity, is disclosed. Additionally, the system embodying a method for network switching of a data packet outgoing from an internal facing interface of a network interface controller portion of the network interface resource to a network is disclosed.

Abstract: A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller, implemented on a chip, to a target entity, is disclosed. Additionally, the system embodying a method for network switching of a data packet outgoing from an internal facing interface of a network interface controller portion of the network interface resource to a network is disclosed.

Abstract: A method and a system embodying the method for a memory address alignment, comprising configuring one or more naturally aligned buffer structure(s); providing a return address pointer in a buffer of one of the one or more naturally aligned buffer structure(s); determining a configuration of the one of the one or more naturally aligned buffer structure(s); applying a modulo arithmetic to the return address and at least one parameter of the determined configuration; and providing a stacked address pointer determined in accordance with the applied modulo arithmetic, is disclosed.

Abstract: A system network switching with layer 2 switch communicatively coupled co-resident data-plane and network interface controllers embodying a method for, receiving a packet from a communication network at the layer 2 switch; parsing the packet; and determining in accordance with a content of the parsed packet whether the packet is to be switched to one of one or more medium access controllers, or one of one or more packet input processors, or one of one or more network interface controllers of a network interface resource comprising the one or more packet input processors, one or more packet output processors, the one or more network interface controllers, and the layer 2 switch, implemented on a chip are disclosed.

Abstract: A method and a system embodying the method for work request arbitration, comprising receiving a work request, the work request indicating one or more groups from a plurality of groups; determining at least one of a plurality of parameters in accordance with the received work request; determining eligibility to provide work among the one or more groups that have work in a work queue in accordance with a first set of the plurality of parameters; and selecting one of the determined eligible groups to provide the work in accordance with a second set of the plurality of parameters is disclosed.

Abstract: A method and a system embodying the method for pre-fetching and processing work for processor cores in a network processor, comprising requesting pre-fetch work by a requestor; determining that the work may be pre-fetched for the requestor; searching for the work to pre-fetch; and pre-fetching the found work into one of one or more pre-fetch work-slots associated with the requestor is disclosed.

Abstract: A method and a system embodying the method for load balancing of a received a packet based network traffic, comprising: receiving a packet at a software defined network switch; determining information pertaining to uniqueness of a packet flow for the received packet; providing the determined information and the received packet to a network interface controller; and processing the received packet at the network interface controller in accordance with the provided determined information, are disclosed.

Abstract: Method and system embodying the method for input/output value determination at a processor core, comprising generating an I/O instruction comprising at least a physical or a virtual address; comparing the address with a relevant database of I/O devices addresses. When the comparing is successful determining the I/O device or a state on the I/O device to receive the I/O instruction in accordance with the address; setting a value of a first register to a value identifying the determined I/O device or the state on the I/O device; predicting a value to be set in a second register in accordance with the address; and setting a value of a third register. Providing I/O instruction other than a request I/O instruction to the I/O device or the state on the I/O device, which sets a register to a value according to the I/O instruction and reports the value to the processor core.

Abstract: A method and a system embodying the method for a data plane virtualization, comprising assigning each of at least one data plane a unique identifier; providing a request comprising an identifier of one of the at least one data plane together with an identifier of a virtual resource assigned to a guest; determining validity of the provided request in accordance with the identifier of the one of the at least one data plane and the identifier of the virtual resource assigned to the guest; and processing the request based on the determined validity of the request are disclosed.

Abstract: A method and an apparatus embodying the method for converting interrupts into scheduled events, comprising receiving an interrupt at an interrupt controller; determining a vector number for the interrupt; determining properties of an interrupt work in accordance with the vector number; and scheduling the interrupt work in accordance with the properties of the interrupt work, is disclosed.