Patents by Inventor Wilson Wong
Wilson Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8767801Abstract: The ability of clock and data recovery (“CDR”) circuitry on an integrated circuit (“IC”) to handle jitter in a serial data input signal can be tested by using transmitter circuitry on the IC to produce a serial data output signal whose time base has been subjected to modulation. Loop-back circuitry on the IC may be used to apply the serial data output signal to the CDR circuitry as the serial data input signal of the CDR circuitry. Modulation circuitry on the IC may be used to cause the above modulation of the time base of the serial data output signal.Type: GrantFiled: March 23, 2010Date of Patent: July 1, 2014Assignee: Altera CorporationInventors: Allen Chan, Wilson Wong
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Patent number: 8754794Abstract: An integrated circuit with a pipeline analog-to-digital (A/D) converter and associated calibration circuitry is provided. The A/D converter may include multiple series-connected pipeline stages at least some of which are implemented using a switched capacitor configuration. The calibration circuitry may include an analog error correction circuit, a digital error correction circuit, and a calibration control circuit for coordinating the operation of the analog and digital error correction circuits. During calibration operations, the analog error correction circuit may be used to suitably adjust a gain setting for each pipeline stage, whereas the digital error correction circuit may be used to compute a code offset value for each pipeline stage. Calibration may proceed from a least-significant-bit pipeline stage towards a most-significant-bit pipeline stage, one stage at a time.Type: GrantFiled: July 25, 2012Date of Patent: June 17, 2014Assignee: Altera CorporationInventors: Wei Li, Weiqi Ding, Wilson Wong
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Patent number: 8743943Abstract: Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.Type: GrantFiled: July 28, 2005Date of Patent: June 3, 2014Assignee: Altera CorporationInventors: Sergey Yuryevich Shumarayev, Wilson Wong, Rakesh Patel
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Patent number: 8699648Abstract: One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.Type: GrantFiled: February 22, 2013Date of Patent: April 15, 2014Assignee: Altera CorporationInventors: Allen Chan, Wilson Wong, Sergey Shumarayev
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Patent number: 8669828Abstract: Integrated circuits with decoupling capacitor circuitry are provided. Decoupling capacitor circuitry may include multiple arrays of decoupling capacitors. Each decoupling capacitor array may have a corresponding decoupling capacitor monitoring circuit that is associated with that decoupling capacitor array. Each decoupling capacitor monitoring circuit may include a resistor and switching circuitry. Each decoupling capacitor monitoring circuit may be coupled to a comparator and control circuitry. During testing, the control circuitry may configure each decoupling capacitor array for leakage current testing one at a time. If a decoupling capacitor array is determined to exhibit excessive leakage currents, that decoupling capacitor array will be marked as defective and will be disabled from use. If the decoupling capacitor array is determined to exhibit tolerable leakage currents, that decoupling capacitor array will be enable for use to help reduce power supply noise.Type: GrantFiled: October 21, 2010Date of Patent: March 11, 2014Assignee: Altera CorporationInventors: Wilson Wong, Allen Chan, Sergey Shumarayev
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Patent number: 8595358Abstract: A configurator is provided that connects with various disparate elements in a telecommunication system. The configurator is adapted to receive a traffic plan that has a plurality of different aspects that are implemented across the disparate elements. The configurator is adapted to generate processing schemas and/or databases that can be used by the disparate elements in order to implement the traffic plan.Type: GrantFiled: March 13, 2008Date of Patent: November 26, 2013Assignee: Redknee Inc.Inventors: John Yuen, Philip Steele, David Cauz, Wilson Wong
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Patent number: 8537954Abstract: The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.Type: GrantFiled: January 15, 2010Date of Patent: September 17, 2013Assignee: Altera CorporationInventors: Sergey Y. Shumarayev, Rakesh H. Patel, Wilson Wong, Tim T. Hoang
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Patent number: 8536919Abstract: Integrated circuits with communications circuitry are provided. The communications circuitry may include at least first and second flip-flops connected in a chain along a data path. The first flip-flop may be controlled by a clock signal. The clock signal may be fed to a delay matching circuit. The delay matching circuit may provide a delayed version of the clock signal that controls the second flip-flop. The delay provided by the delay matching circuit may be equal to a clock-to-output delay of the first flip-flop. The delay matching circuit may have the same physical arrangement as the first flip-flop. The first and second flip-flops and the delay matching circuit may include dynamic sense amplifier flip-flops. The delay matching circuit may have an input that receives a high signal, a control input that receives the clock signal, and an output over which the delayed clock signal is provided.Type: GrantFiled: October 21, 2010Date of Patent: September 17, 2013Assignee: Altera CorporationInventors: Allen Chan, Wilson Wong
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Patent number: 8446172Abstract: One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.Type: GrantFiled: May 6, 2011Date of Patent: May 21, 2013Assignee: Altera CorporationInventors: Allen Chan, Wilson Wong
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Patent number: 8416845Abstract: Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.Type: GrantFiled: July 11, 2006Date of Patent: April 9, 2013Assignee: Altera CorporationInventors: Wilson Wong, Sergey Yuryevich Shumarayev, Rakesh Patel, Tim Tri Hoang
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Patent number: 8416001Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.Type: GrantFiled: April 8, 2011Date of Patent: April 9, 2013Assignee: Altera CorporationInventors: Weiqi Ding, Sergey Shumarayev, Wilson Wong, Tim Tri Hoang, Yanjing Ke
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Patent number: 8406258Abstract: One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer.Type: GrantFiled: April 1, 2010Date of Patent: March 26, 2013Assignee: Altera CorporationInventors: Wilson Wong, Tim Tri Hoang, Thungoc M. Tran, Sergey Shumarayev, Allen Chan
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Patent number: 8385496Abstract: One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.Type: GrantFiled: October 21, 2010Date of Patent: February 26, 2013Assignee: Altera CorporationInventors: Allen Chan, Wilson Wong, Sergey Shumarayev
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Publication number: 20130009279Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Inventors: Weiqi Ding, Sergey Shumarayev, Wilson Wong, Ali Atesoglu, Sharat Babu Ippili
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Patent number: 8335249Abstract: Equalizer circuitry on an integrated circuit (“IC”) includes first, second, and third continuous time, equalizer stages connected in series. Each stage includes peaking inductor circuitry. The equalizer circuitry may further include controllably variable, static, DC mode offset voltage compensation circuitry and/or dynamic, continuous mode, offset voltage compensation circuitry for respectively reducing DC voltage offset and/or time-varying, continuous mode voltage offset between an output of the third equalizer stage and utilization circuitry to which that output is applied. The first equalizer stage may be preceded by termination circuitry having controllably variable impedance. Differential circuitry and signalling may be used for various circuit components. The equalizer circuitry is particularly useful for fabrication as part of a programmable IC, using 28 nm CMOS technology, and as a receiver equalizer for a high-speed serial data signal having a bit rate of 20-25 Gbps.Type: GrantFiled: November 25, 2009Date of Patent: December 18, 2012Assignee: Altera CorporationInventors: Xiaoyan Su, Sriram Narayan, Wilson Wong, Sergey Shumarayev
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Patent number: 8319564Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.Type: GrantFiled: March 26, 2010Date of Patent: November 27, 2012Assignee: Altera CorporationInventors: Weiqi Ding, Sergey Shumarayev, Wilson Wong, Ali Atesoglu, Sharat Babu Ippili
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Publication number: 20120280724Abstract: One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.Type: ApplicationFiled: May 6, 2011Publication date: November 8, 2012Inventors: Allen CHAN, Wilson WONG
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Patent number: 8299802Abstract: An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.Type: GrantFiled: October 31, 2008Date of Patent: October 30, 2012Assignee: Altera CorporationInventors: Wilson Wong, Allen Chan, Sergey Shumarayev
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Patent number: 8290750Abstract: Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.Type: GrantFiled: February 28, 2011Date of Patent: October 16, 2012Assignee: Altera CorporationInventors: Wilson Wong, Allen Chan, Sergey Shumarayev, Thungoc M. Tran, Tim Tri Hoang, Weiqi Ding
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Publication number: 20120256670Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.Type: ApplicationFiled: April 8, 2011Publication date: October 11, 2012Applicant: ALTERA CORPORATIONInventors: Weiqi Ding, Sergey Shumarayev, Wilson Wong, Tim Tri Hoang, Yanjing Ke