Abstract: A single servo control loop for amplifier gain control based on signal power change over time or system to system, having an amplifier configured to receive an input signal on an amplifier input and generate an amplified signal on an amplifier output. The differential signal generator processes the amplified signal to generate differential output signals. The single servo control loop processes the differential output signal to generates one or more gain control signals and one or more current sink control signals. A gain control system receives a gain control signal and, responsive thereto, controls a gain of one or more amplifiers. A current sink receives a current sink control signal and, responsive thereto, draws current away from the amplifier input. Changes in input power ranges generate changes in the integration level of the differential signal outputs which are detected by the control loop, and responsive thereto, the control loop dynamically adjusts the control signals.

Abstract: A single servo control loop for amplifier gain control based on signal power change over time or system to system, having an amplifier configured to receive an input signal on an amplifier input and generate an amplified signal on an amplifier output. The differential signal generator processes the amplified signal to generate differential output signals. The single servo control loop processes the differential output signal to generates one or more gain control signals and one or more current sink control signals. A gain control system receives a gain control signal and, responsive thereto, controls a gain of one or more amplifiers. A current sink receives a current sink control signal and, responsive thereto, draws current away from the amplifier input. Changes in input power ranges generate changes in the integration level of the differential signal outputs which are detected by the control loop, and responsive thereto, the control loop dynamically adjusts the control signals.

Abstract: There is provided a voltage mode push-pull driver output stage with low power consumption and improved output return loss (ORL) suitable for various high bandwidth data transmission applications. By structuring the output stage to have tunable resistances adjustable by voltages applied to transistors, the output stage is readily adaptable to different applications requiring different resistances or impedance matching.

Abstract: There is provided a voltage mode push-pull driver output stage with low power consumption and improved output return loss (ORL) suitable for various high bandwidth data transmission applications. By structuring the output stage to have tunable resistances adjustable by voltages applied to transistors, the output stage is readily adaptable to different applications requiring different resistances or impedance matching.

Abstract: A trans-impedance amplifier receives an input current and is operable to generate an output voltage responsive to the input current. The amplifier is responsive to an increased range of input currents and has a wide bandwidth. The amplifier includes an input stage having a first and a second transistor and is configured to receive the input current. The amplifier includes an output stage coupled to the input stage and having a third and a fourth transistor. A variable resistor is coupled to the output stage to adjust the amount of current in the output stage. A variable current source is coupled to the output stage and is operable to adjust the amount of current in the output stage. A output driver, which is coupled to the output stage, includes at least another transistor. The output driver is operable to provide the output voltage and is operable to reduce the output impedance of the amplifier.

Abstract: A trans-impedance amplifier receives an input current and is operable to generate an output voltage responsive to the input current. The amplifier is responsive to an increased range of input currents and has a wide bandwidth. The amplifier includes an input stage having a first and a second transistor and is configured to receive the input current. The amplifier includes an output stage coupled to the input stage and having a third and a fourth transistor. A variable resistor is coupled to the output stage to adjust the amount of current in the output stage. A variable current source is coupled to the output stage and is operable to adjust the amount of current in the output stage. A output driver, which is coupled to the output stage, includes at least another transistor. The output driver is operable to provide the output voltage and is operable to reduce the output impedance of the amplifier.

Abstract: A method and apparatus for signal amplification and decision device operation on a signal which has a magnitude, peak value, or other average power that varies over time. In general, a peak detector detects the peak value of a received signal and responsive to the peak value, selectively enables a decision device when the signal is amplified to increase decision device accuracy. The decision may occur before the amplification forces the signal into saturation. Multi-stage amplification in combination with controlled switching or multiplexing may be utilized to selectively IO amplify the signal and selectively initiate decision device operation. The peak detector value may also control signal amplification levels in a multi-stage amplifier. Responsive to the peak value, a switch, which receives as its input the output from one or more amplifier stages, may be controlled to output the signal after a desired amount of amplification.

Abstract: Various systems and methods for automatic data rate detection are provided. In one embodiment, a system is provided that includes a clock and data recovery circuit embodied in a first integrated circuit, the clock and data recovery circuit being configured to re-clock a data stream. The system also includes an automatic rate detection system embodied in a second integrated circuit, where the first integrated circuit is in data communication with the second integrated circuit. Also, the automatic rate detection system is configured to determine a data rate of the data stream upon identifying a transition in the data rate of the data stream based upon the state of the at least one status flag received from the clock and data recovery circuit.

Abstract: A multiple channel signal processing circuit receives an input associated with a first channel and an input associated with a second channel. The respective inputs are sampled and processed by the circuit, which generates a sampled output signal for the first channel and a sampled output signal for the second channel. The circuit employs a shared active circuit component, such as an operational amplifier, to alternately process samples associated with the first and second channels. A network of switches are controlled by a multiphase clock signal such that the active circuit component processes samples associated with only one channel at a time; as the input for a first channel is being sampled, a previous sample for the second channel is processed. An alternate circuit embodiment may be utilized to reduce the amount of crosstalk between the channels.