Abstract: An automation server accesses a task for a robotic device. The automation server generates motor control commands for the robotic device to complete the task. The automation server transmits, via a network and in a format defined by an Application Program Interface (API), the motor control commands from the automation server to a fleet manager associated with the robotic device, the motor control commands for forwarding from the fleet manager to the robotic device. The automation server receives, from one or more sensors attached to the robotic device and via the network, robotic device sensor data. The automation server receives, from multiple remote sensors and via the network, remote sensor data. The automation server adjusts the generated motor control commands to complete the task based on the robotic device sensor data and the remote sensor data.

Abstract: An automation server accesses a task for a robotic device. The automation server generates motor control commands for the robotic device to complete the task. The automation server transmits, via a network and in a format defined by an Application Program Interface (API), the motor control commands from the automation server to a fleet manager associated with the robotic device, the motor control commands for forwarding from the fleet manager to the robotic device. The automation server receives, from one or more sensors attached to the robotic device and via the network, robotic device sensor data. The automation server receives, from multiple remote sensors and via the network, remote sensor data. The automation server adjusts the generated motor control commands to complete the task based on the robotic device sensor data and the remote sensor data.

Abstract: A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during the processing, yet be separated therefrom upon room temperature peeling force that leaves the thinner one of the thin sheet and carrier intact. Interposers (56) having arrays (50) of vias (60) may be formed on the thin sheet, and devices (66) formed on the interposers. Alternatively, the thin sheet may be a substrate on which semiconductor circuits are formed during FEOL processing.

Abstract: A flexible glass laminate structure includes a flexible glass substrate having a thickness of no more than 0.3 mm. The flexible glass laminate structure includes a flexible glass layer including the flexible glass substrate. A property control layer is laminated to the flexible glass layer. A neutral axis of the flexible glass laminate is located outside the flexible glass layer when the flexible glass layer is in a compressive bend configuration.

Abstract: A flexible glass laminate structure includes a flexible glass substrate having a thickness of no more than 0.3 mm. The flexible glass laminate structure includes a flexible glass layer including the flexible glass substrate. A property control layer is laminated to the flexible glass layer. A neutral axis of the flexible glass laminate is located outside the flexible glass layer when the flexible glass layer is in a compressive bend configuration.

Abstract: A non-polished glass wafer, a thinning system, and a method for using the non-polished glass wafer to thin a semiconductor wafer are described herein. In one embodiment, the glass wafer has a body (e.g., circular body) including a non-polished first surface and a non-polished second surface substantially parallel to each other. In addition, the circular body has a wafer quality index which is equal to a total thickness variation in micrometers plus one-tenth of a warp in micrometers that is less than 6.0.

Abstract: An assembly, such as for growing carbon nanotubes, includes a substrate including SiO2 and has a thickness of less than 500 ?m. Further, the substrate is bendable and has a surface with non-flat or non-polished texture such that surface comprises raised and recessed features for receiving a coating, such as a catalyst. Carbon nanotubes may be anchored to and grow from the recessed features of the substrate.

Abstract: A non-polished glass wafer, a thinning system, and a method for using the non-polished glass wafer to thin a semiconductor wafer are described herein. In one embodiment, the glass wafer has a body (e.g., circular body) including a non-polished first surface and a non-polished second surface substantially parallel to each other. In addition, the circular body has a wafer quality index which is equal to a total thickness variation in micrometers plus one-tenth of a warp in micrometers that is less than 6.0.

Abstract: An assembly, such as for growing carbon nanotubes, includes a substrate including SiO2 and has a thickness of less than 500 ?m. Further, the substrate is bendable and has a surface with non-flat or non-polished texture such that surface comprises raised and recessed features for receiving a coating, such as a catalyst. Carbon nanotubes may be anchored to and grow from the recessed features of the substrate.

Abstract: A non-polished glass wafer, a thinning system, and a method for using the non-polished glass wafer to thin a semiconductor wafer are described herein. In one embodiment, the glass wafer has a body (e.g., circular body) including a non-polished first surface and a non-polished second surface substantially parallel to each other. In addition, the circular body has a wafer quality index which is equal to a total thickness variation in micrometers plus one-tenth of a warp in micrometers that is less than 6.0.

Abstract: A three-dimensional integrated circuit (3D-IC) which incorporates a glass interposer and a method for fabricating the three-dimensional integrated circuit (3D-IC) with the glass interposer are described herein. In one embodiment, the 3D-IC incorporates a glass interposer which has vias formed therein which are not filled with a conductor that allow for precision metal-to-metal interconnects (for example) between redistribution layers. In another embodiment, the 3D-IC incorporates a glass interposer which has vias and has a coefficient of thermal expansion (CTE) that is different than the CTE of silicon which is 3.2 ppm/° C.

Abstract: A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during the processing, yet be separated therefrom upon room temperature peeling force that leaves the thinner one of the thin sheet and carrier intact. Interposers (56) having arrays (50) of vias (60) may be formed on the thin sheet, and devices (66) formed on the interposers. Alternatively, the thin sheet may be a substrate on which semiconductor circuits are formed during FEOL processing.

Abstract: A three-dimensional integrated circuit (3D-IC) which incorporates a glass interposer and a method for fabricating the three-dimensional integrated circuit (3D-IC) with the glass interposer are described herein. In one embodiment, the 3D-IC incorporates a glass interposer which has vias formed therein which are not filled with a conductor that allow for precision metal-to-metal interconnects (for example) between redistribution layers. In another embodiment, the 3D-IC incorporates a glass interposer which has vias and has a coefficient of thermal expansion (CTE) that is different than the CTE of silicon which is 3.2 ppm/° C.

Abstract: A non-polished glass wafer, a thinning system, and a method for using the non-polished glass wafer to thin a semiconductor wafer are described herein. In one embodiment, the glass wafer has a body (e.g., circular body) including a non-polished first surface and a non-polished second surface substantially parallel to each other. In addition, the circular body has a wafer quality index which is equal to a total thickness variation in micrometers plus one-tenth of a warp in micrometers that is less than 6.0.