Abstract: A battery system for a vehicle includes: first and second positive terminals and a negative terminal; switches; at least three strings of battery cells, each of the strings configured to, at different times be: connected to the first positive terminal via first ones of the switches; connected to the second positive terminal via second ones of the switches; and disconnected from both of the first and second positive terminals; and a switch control module configured to: identify one of a short circuit and an over voltage condition in a first voltage bus; when the one of the short circuit and the over voltage condition is identified, identify N of the strings of battery cells with the N lowest state of health values; and control switching of the switches and connect the identified N strings of battery cells to the first voltage bus.

Abstract: A low-voltage mitigation and recovery system includes: an auxiliary power module that converts an output voltage of a power source of a vehicle to a charging voltage, the power source provides power to power a propulsion system of the vehicle; a contactor that supplies power from the power source to the auxiliary power module; a first control module that controls states of the auxiliary power module and the contactor. A second control module is integrated within a MODACS, monitors parameters of blocks of cells of the MODACS, and, based on at least one of the parameters: configures a switch network of the MODACS to disconnect a first set of blocks of the MODACS from loads and to connect or maintain connection of a second set of blocks of the MODACS to selected ones of the loads; and wakes up the first control module to jump start and recover the MODACS.

Abstract: A decision feedback equalizer (DFE) sampler circuit is disclosed. The DFE sampler includes a front-end circuit configured to generate a filtered signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols and a summing circuit configured to generate an equalized signal by combining the filtered signal and an analog feedback signal based on a digital feedback signal. The DFE sampler further includes first and second samplers configured to sample the equalized signal and generate first and second regeneration signals, respectively, during first and second time periods. A compensation circuit is configured to generate the digital feedback signal using the first and second regeneration signals. The first and second samplers, in alternating time periods, cancel ISI from the equalized signal using the first and second regeneration signals, respectively.

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Abstract: An integrated circuit is disclosed. The integrated circuit includes an equalizer circuit that may provide high-frequency signal amplification. The equalizer circuit also has adjustable impedance circuitry, which may receive digital control signals to adjust the effective impedance of the equalizer circuit. Furthermore, a method of operating the equalizer circuit is also disclosed.

Abstract: One embodiment relates to an apparatus for regulating a voltage-controlled oscillator. The apparatus includes a digital-to-analog converter that has an input that receives a digital input signal and an output that outputs an analog control signal. A transistor receives the analog control signal so as to control an output voltage of the voltage-controlled oscillator. Control circuitry receives the output voltage and generates the digital input signal. Another embodiment relates to a method of regulating a voltage-controlled oscillator. A digital input signal is converted to an analog control signal using a digital-to-analog converter. The output voltage of the voltage-controlled oscillator is controlled using the analog control signal and monitored using a plurality of comparators. The digital input signal is changed depending on outputs of the plurality of comparators. Other embodiments, aspects, and features of the invention are also disclosed.

Abstract: One embodiment relates to an equalizer circuit for a data link. The equalizer circuit including a continuous-time linear equalizer, a first circuit loop, and a second circuit loop. The continuous-time linear equalizer receives a received signal and outputs an equalized signal. The first circuit loop determines a first average signal amplitude. The first average signal amplitude may be an average signal amplitude of the equalized signal. The second circuit loop a second average signal amplitude. The second average signal amplitude may be an average signal amplitude of a high-frequency portion of the equalized signal. Other embodiments and features are also disclosed.

Abstract: In an embodiment of the present invention, a feedback technique is used to track a reference signal with a DFE summing node common mode voltage. For example, in an embodiment implemented in CML, the feedback signal shifts both differential signals (e.g., the summing node common voltage and the reference voltage) by the same amount. In such an embodiment, the feedback technique preferably changes the reference common mode but not its differential mode.

Abstract: The present invention relates to a hand held cutter (11) utilizing auxiliary wheels (9) individually performing two working modes including cuts along a rectilinear path and a desired curved path. By switching a control, a pair of auxiliary wheels (9) shifts the cutter (11) from one working mode to one another. According to the unique design of the present invention, a circular disk-shaped cutting blade (14) mounted on the side edge of the pair of auxiliary wheels (9) can produce a stable and versatile cutting effects under the guidance of the auxiliary wheels (9). The application and breakthrough of technologies reduce the size of the hand held cutter (11) so that the cutter 11 can be conveniently carried around.

Abstract: The present invention relates to a hand held cutter (11) utilizing auxiliary wheels (9) individually performing two working modes including cuts along a rectilinear path and a desired curved path. By switching a control, a pair of auxiliary wheels (9) shifts the cutter (11) from one working mode to one another. According to the unique design of the present invention, a circular disk-shaped cutting blade (14) mounted on the side edge of the pair of auxiliary wheels (9) can produce a stable and versatile cutting effects under the guidance of the auxiliary wheels (9). The application and breakthrough of technologies reduce the size of the hand held cutter (11) so that the cutter 11 can be conveniently carried around.

Abstract: Fluorescent dyes based on rhodamine are derivatized to form labeled conjugates that fluoresce upon excitation with light of an appropriate wavelength. Particularly preferred embodiments are certain single isomer form rhodamine phosphoramidites. These rhodamine phosphoramidites enhance the efficiency of synthesizing rhodamine-labeled oligonucleotides by solid phase methods. Conjugate embodiments of the invention are prevented from being converted to a non-fluorescent lactam form due to having a fully substituted amide linkage derived from the 3-position carboxylate.