Abstract: Using an electronically scanned phased array antenna, a technique is developed for aligning a broad elevation beam along an isodop for use in synthetic aperture mapping. A beam steering controller algorithm for practical implementation of the technique is described. Implementation is realized by means of a beam steering controller and the radar computer. The controller first finds the space stabilized row and column for a given phase shifter. A look-up table furnished by the radar controller provides a slope correction as a function of row. The slope is multiplied by the element column to give the correct linear phase function. This term is then subtracted from the term used to point the beam peak.

Abstract: A programmable transform processor apparatus is disclosed which has an input and output for receiving and transmitting data and a data storage hardware for storing input data, as well as intermediate transform results. Arithmetic processing hardware processes input signals and has a multiplier accumulator having the multiplication function performed as a sequence of products combined in the accumulator portion of the multiplier accumulator simultaneous with the accumulator, accumulating the sum of the products therein. Data control hardware is operatively connected to the input/output means and to the data storage means and the arithmetic processing means for controlling the input and output of data for the input and output and the operation of the arithmetic processing hardware and the control of data to and from the data storage hardware.

Abstract: A pipeline processor of a radix-2 configuration including an input, intermediate and output processing sections for performing a discrete Fourier transformation (DFT) of an input array of N signal values to derive an output array of at least N signal values representative of the frequency transformation of the input array is disclosed. The input and output processing sections include first and second pluralities of cascadedly coupled computational elements respectively, which are governed to perform computations in a pipeline fashion and to propagate resulting interelement computed signal values through the input section in a first predetermined signal flow pattern and through the output section in a second predetermined signal flow pattern to render respectively a first intermediate array and the output array of signal values.

Abstract: A signal processor and method for processing N discrete samples of a quantized time domain signal to determine the frequency content or frequency spectrum of the time domain signal. Real and imaginary components of the quantized signal are processed in accordance with a decomposition technique that eliminates considerable hardware and reduces processing time. In a multiple stage processor, interstage multipliers are eliminated. One such disclosed processor includes a first data memory stage for storing the discrete samples of the quantized time domain signal and for retrieving the stored samples in a predetermined order in which component positions are circularly rotated by a predetermined number of positions from the order of storage thereof. An L-point computational stage receives the retrieved samples of the quantized time domain signal and calculates real and imaginary output signals representing the solution to an L-point discrete Fourier transform.

Abstract: A digital processor comprising a network of arithmetic units and including apparatus for detecting and isolating a static bit fault therein is disclosed. A plurality of first arithmetic units of the network employ non-linear type operations. Each of the first arithmetic units arithmetically operate on a corresponding number of the binary coded digital input words of the network to produce a first output binary coded digital word which is coupled to the remaining network of arithmetic units. Corresponding to each of the first arithmetic units, there is provided a modulo 3 model to emulate in modulo 3 arithmetic the operation thereof and to compare the result of the modulo 3 emulation with the modulo 3 equivalent of a preselected word from the corresponding first arithmetic unit, the preselected word being intermediate the non-linear operation performed thereby. A non-equivalence condition resulting from the comparison is indicative of a static bit fault.