Patents by Inventor Wiren Dale Becker
Wiren Dale Becker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136270Abstract: An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.Type: ApplicationFiled: October 23, 2022Publication date: April 25, 2024Inventors: Francesco PREDA, Sungjun CHUN, Jose A. HEJASE, Junyan TANG, Pavel ROY PALADHI, Nam Huu PHAM, Wiren Dale BECKER, Daniel Mark DREPS
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Publication number: 20240008186Abstract: A gang drilling machine for drilling a circuit card includes a pair of n and p master drills that are configured to be aligned in registry with respective n and p test vias of the card; pluralities of n and p minion drills that are configured to be aligned in registry with pluralities of n and p live vias of the card; and a controller that is electrically connected to control the n and p master drills and minion drills, and to send and receive electrical signals to and from the card. The controller is configured to: send a query signal to the card; monitor a response signal from the card; determine drilling depth of at least one of the master drills, in response to comparing the response signal to the query signal; and adjust operation of the machine, in response to the determined drilling depth.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Yanyan Zhang, Mahesh Bohra, Wiren Dale Becker, Nam Huu Pham, Pavel Roy Paladhi, Daniel Mark Dreps, Lloyd Andre Walls
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Patent number: 11133259Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.Type: GrantFiled: December 12, 2019Date of Patent: September 28, 2021Assignee: International Business Machines CorporationInventors: Joshua M. Rubin, Arvind Kumar, Lawrence A. Clevenger, Steven Lorenz Wright, Wiren Dale Becker, Xiao Hu Liu
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Publication number: 20210183773Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.Type: ApplicationFiled: December 12, 2019Publication date: June 17, 2021Inventors: Joshua M. Rubin, Arvind Kumar, Lawrence A. Clevenger, Steven Lorenz Wright, Wiren Dale Becker, Xiao Hu Liu
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Publication number: 20170053899Abstract: In an integrated chip stack arrangement, wherein power is provided to an upper integrated chip, including a processor core with a grid arrangement of cells connected to a power supply in a substrate by a conventional C4 solder ball array on the substrate connected through TSVs in an intermediate integrated circuit chip, it has been recognized that for maximum current efficiency and minimum electro migration the vias should not be directly coincident with the micro C4 solder balls connecting the upper chip with the intermediate chip.Type: ApplicationFiled: March 1, 2016Publication date: February 23, 2017Inventors: Gerald K. Bartley, Wiren Dale Becker, Andreas Huber, Tingdong Zhou
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Publication number: 20160071822Abstract: In an integrated chip stack arrangement, wherein power is provided to an upper integrated chip, including a processor core with a grid arrangement of cells connected to a power supply in a substrate by a conventional C4 solder ball array on the substrate connected through TSVs in an intermediate integrated circuit chip, it has been recognized that for maximum current efficiency and minimum electro migration the vias should not be directly coincident with the micro C4 solder balls connecting the upper chip with the intermediate chip.Type: ApplicationFiled: September 8, 2014Publication date: March 10, 2016Inventors: Gerald K. Bartley, Wiren Dale Becker, Andreas Huber, Tingdong Zhou
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Patent number: 8683413Abstract: A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below and adjacent to the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas The Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.Type: GrantFiled: September 15, 2012Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Wiren Dale Becker, Jinwoo Choi, Tingdong Zhou
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Patent number: 8339803Abstract: A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.Type: GrantFiled: December 4, 2009Date of Patent: December 25, 2012Assignee: International Business Machine CorporationInventors: Wiren Dale Becker, Jinwoo Choi, Tingdong Zhou
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Patent number: 8261226Abstract: A scaled network flow graph is constructed, including a plurality of nodes and a plurality of edges. The plurality of nodes correspond to: (i) a pseudo device pin node for each pair of corresponding paired device pins; (ii) a pseudo bottom surface metal node for each pair of bottom surface metal pins on each of multiple routing layers; (iii) a source node connected to each of the pseudo device pin nodes; (iv) a sub-sink node for each pair of the paired bottom surface metal pins (each of the sub-sink nodes is connected to corresponding ones of the pseudo bottom surface metal nodes for each of the pairs of bottom surface metal pins on each of the multiple routing layers); and (v) a sink node connected to the sub-sink nodes. A capacity and a cost are assigned to each of the edges of the scaled network flow graph. A min-cost-max-flow technique is applied to the scaled network flow graph with the assigned capacities and costs to obtain an optimal flow solution.Type: GrantFiled: July 20, 2011Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventors: Wiren Dale Becker, Ruchir Puri, Haoxing Ren, Hua Xiang, Tingdong Zhou
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Patent number: 7987587Abstract: A method is described by which an electrical path is created between layers on a printed circuit board (PCB) without the use of plated through holes (PTH). Through the use of a liquid solder or conductive epoxy injection fixture, a conductive path is created in pre-drilled holes forming an electrical connection between internal PCB metal layers and surface mounted components without the creation of parasitic stubs on the signal nets.Type: GrantFiled: March 7, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Wiren Dale Becker, Michael Ford McAllister, Alan Daniel Stigliani, John G. Torok
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Publication number: 20110010482Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.Type: ApplicationFiled: September 20, 2010Publication date: January 13, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wiren Dale Becker, Daniel Mark Dreps, Frank David Ferraiolo, Anand Haridass, Robert James Reese
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Patent number: 7813266Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.Type: GrantFiled: November 30, 2007Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Wiren Dale Becker, Daniel Mark Dreps, Frank David Ferraiolo, Anand Haridass, Robert James Reese
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Publication number: 20100085872Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.Type: ApplicationFiled: December 10, 2009Publication date: April 8, 2010Applicant: International Business Machines CorporationInventors: Wiren Dale Becker, Daniel Mark Dreps, Frank David Ferraiolo, Anand Haridass, Robert James Reese
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Publication number: 20090223710Abstract: A method is described by which an electrical path is created between layers on a printed circuit board (PCB) without the use of plated through holes (PTH). Through the use of a liquid solder or conductive epoxy injection fixture, a conductive path is created in pre-drilled holes forming an electrical connection between internal PCB metal layers and surface mounted components without the creation of parasitic stubs on the signal nets.Type: ApplicationFiled: March 7, 2008Publication date: September 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wiren Dale Becker, Michael Ford McAllister, Alan Daniel Stigliani, John G. Torok
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Patent number: 7382844Abstract: A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.Type: GrantFiled: February 11, 2005Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Charlie C. Hwang, Timothy G. McNamara, Ching-Lung Tong, Wiren Dale Becker
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Patent number: 7362697Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.Type: GrantFiled: January 9, 2003Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Wiren Dale Becker, Daniel Mark Dreps, Frank David Ferraiolo, Anand Haridass, Robert James Reese
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Patent number: 7284992Abstract: Apparatus and methods are provided for constructing electronic package structures using LGA (land grid array) module-to-board connectors that are designed to provide higher count I/O interconnections by expanding LGA area, but without having to increase chip module footprint or reduce the pitch of area array I/O contacts of an LGA interposer or circuit board beyond practical limits.Type: GrantFiled: March 22, 2006Date of Patent: October 23, 2007Assignee: International Business Machines CorporationInventors: Wiren Dale Becker, William Louis Brodsky, Evan George Colgan, Michael Ford McAllister, Edward Seminaro, John Torok
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Patent number: 7233170Abstract: Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an N×1 MUX. The N×1 MUX is controlled by the skew controller. The output of the N×1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.Type: GrantFiled: August 25, 2005Date of Patent: June 19, 2007Assignee: International Business Machines CorporationInventors: Wiren Dale Becker, Anand Haridass, Bao G. Truong
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Patent number: 6774836Abstract: A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.Type: GrantFiled: June 16, 2003Date of Patent: August 10, 2004Assignee: International Business Machines CorporationInventors: Roland Frech, Bernd Garben, Hubert Harrer, Andreas Huber, Dierk Kaller, Erich Klink, Thomas-Michael Winkel, Wiren Dale Becker
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Publication number: 20040136319Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.Type: ApplicationFiled: January 9, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: Wiren Dale Becker, Daniel Mark Dreps, Frank David Ferraiolo, Anand Haridass, Robert James Reese