Patents by Inventor Wojciech Wasko
Wojciech Wasko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154783Abstract: In one embodiment, a system includes a network interface controller to receive a first clock-synchronization message from a clock-synchronization leader device and send a second clock-synchronization messages to at least one clock-synchronization follower device, and a processor to execute software to generate the second clock-synchronization message, and generate a control dependency to condition sending the second clock-synchronization message by the network interface controller to the at least one clock-synchronization follower device on the network interface controller receiving the first clock-synchronization message from the clock-synchronization leader device.Type: ApplicationFiled: November 9, 2022Publication date: May 9, 2024Inventors: Dotan David Levi, Wojciech Wasko
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Publication number: 20240146431Abstract: In one embodiment, a system includes a network interface controller including a device interface to connect to a processing device and receive a time synchronization marker message from an application running on the processing device, a network interface to send packets over a network, and packet processing circuitry to process the time synchronization marker message for sending via the network interface over the network to a slave clock device, generate a time synchronization follow-up message including a timestamp indicative of when the synchronization marker message egressed the network interface, and process the time synchronization follow-up message for sending via the network interface over the network to the slave clock device.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Inventors: Wojciech Wasko, Dotan David Levi, Avi Urman, Natan Manevich
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Publication number: 20240089077Abstract: A network interface device includes a local register and packet processing circuitry coupled to the local register. The packet processing circuitry is to: capture a network packet transmitted by a software application running on an integrated computing system; capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities that are running on the integrated computing system; store the receive timestamp in the local register; associate the receive timestamp from the local register with a first packet copy of the network packet; insert the first packet copy to a first receive pipeline of a first subscriber entity; associate the receive timestamp from the local register with a second packet copy of the network packet; and insert the second packet copy to a second receive pipeline of a second subscriber entity.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Wojciech Wasko, Dotan David Levi, Natan Manevich, Maciek Machnikowski
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Patent number: 11917045Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.Type: GrantFiled: July 24, 2022Date of Patent: February 27, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Arnon Sattinger, Natan Manevich, Wojciech Wasko, Ariel Almog, Bar Or Shapira
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Publication number: 20240064443Abstract: Systems, devices, and methods are described herein for reducing a link bringup time period for optical switching between network devices. An example method of the present disclosure receives an indication of a reconfiguration condition associated with an optical switch communicatively coupled to an optical communication channel and based on the reconfiguration condition, selects first data associated with a storage device or second data associated with a pattern generator device for transmission to a first network device. Selecting the first or second data may be based on a digital logic signal that indicates whether data is actively received from the second network device via the optical communication channel or may be based on a defined schedule for reconfiguring the optical switch.Type: ApplicationFiled: September 20, 2022Publication date: February 22, 2024Inventors: Ioannis (Giannis) Patronas, Paraskevas Bakopoulos, Dotan David Levi, Aviv Berg, Wojciech Wasko, Dimitrios Syrivelis, Elad Mentovich, Yoav Rozenberg, Nikolaos Argyris
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Patent number: 11907754Abstract: In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.Type: GrantFiled: December 14, 2021Date of Patent: February 20, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Wojciech Wasko, Dotan David Levi, Liron Mula, Natan Manevich
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Publication number: 20240031121Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.Type: ApplicationFiled: July 24, 2022Publication date: January 25, 2024Inventors: Dotan David Levi, Arnon Sattinger, Natan Manevich, Wojciech Wasko, Ariel Almog, Bar Or Shapira
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Publication number: 20240031124Abstract: In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Inventors: Dotan David Levi, Wojciech Wasko, Natan Manevich
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Publication number: 20240015419Abstract: Network devices and associated methods are provided for synchronization in an optically switched network. The network device includes one or more ports in communication with a plurality of devices via an optical switch. The one or more ports receive a master clock signal having a first frequency from a first device of the plurality of devices. The network device includes a local clock in communication with the one or more ports and operating at a second frequency. The network device includes a synchronization manager in communication with the one or more ports and the local clock and configured to be enabled and disabled. When the synchronization manager is enabled, it receives the master clock signal via the one or more ports and transmits an instruction to the local clock to operate at the first frequency.Type: ApplicationFiled: July 21, 2022Publication date: January 11, 2024Inventors: Ioannis (Giannis) Patronas, Dotan David Levi, Wojciech Wasko, Paraskevas Bakopoulos, Dimitrios Syrivelis, Elad Mentovich
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Patent number: 11853116Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.Type: GrantFiled: January 24, 2022Date of Patent: December 26, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Wojciech Wasko, Eitan Zahavi, Natan Manevich, Bar Shapira
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Publication number: 20230370305Abstract: In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.Type: ApplicationFiled: August 11, 2022Publication date: November 16, 2023Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Publication number: 20230367358Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.Type: ApplicationFiled: July 19, 2022Publication date: November 16, 2023Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Patent number: 11757614Abstract: In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.Type: GrantFiled: May 10, 2021Date of Patent: September 12, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Wojciech Wasko, Natan Manevich, Teferet Geula, Amit Mandelbaum, Ariel Almog
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Publication number: 20230269684Abstract: A network adapter comprises an output that couples to a central processing unit (CPU) of a network device, a first clock coupled to the output and configured to be synchronized with a second clock that is external to the CPU and the network adapter, and circuitry coupled to the first clock. The circuitry is configured to generate, using the synchronized first clock, a tick at a time offset from a timeslot of a radio schedule for a radio unit and send the tick to the output.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Inventors: Wojciech Wasko, Dotan David Levi, Natan Manevich, Timothy James Martin
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Publication number: 20230251899Abstract: In one embodiment, a system includes a peripheral device including a hardware clock, and processing circuitry to read a given work request entry stored with a plurality of work request entries in at least one work queue in a memory, the given work request entry including timing data and an operator, the timing data being indicative of a time at which a work request should be executed, retrieve a clock value from the hardware clock, and execute the work request with a workload while execution of the work request is timed responsively to the timing data and the operator and the retrieved clock value.Type: ApplicationFiled: February 9, 2022Publication date: August 10, 2023Inventors: Dotan David Levi, Daniel Marcovitch, Natan Manevich, Wojciech Wasko, Igor Voks
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Publication number: 20230236624Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.Type: ApplicationFiled: January 24, 2022Publication date: July 27, 2023Inventors: Dotan David Levi, Wojciech Wasko, Eitan Zahavi, Natan Manevich, Bar Shapira
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Publication number: 20230239068Abstract: A network adapter includes a host interface and a scheduler. The host interface is configured to receive, from one or more hosts, packets for transmission to respective destinations over a network. The scheduler is configured to synchronize to a time-division schedule that is employed in the network, the time-division schedule specifying (i) multiple time-slots and (ii) multiple respective groups of the destinations that are reachable during the time-slots, and, based on the time-division schedule, to schedule transmission times of the packets to the network on time-slots during which the respective destinations of the packets are reachable.Type: ApplicationFiled: February 7, 2022Publication date: July 27, 2023Inventors: Dotan David Levi, Ioannis (Giannis) Patronas, Wojciech Wasko, Paraskevas Bakopoulos, Dimitrios Syrivelis, Elad Mentovich
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Patent number: 11711158Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.Type: GrantFiled: June 28, 2021Date of Patent: July 25, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Wojciech Wasko, Natan Manevich, Hillel Chapman, Roi Geuli, Eyal Serbro
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Publication number: 20230231695Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.Type: ApplicationFiled: January 20, 2022Publication date: July 20, 2023Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Patent number: 11706014Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.Type: GrantFiled: January 20, 2022Date of Patent: July 18, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira