Patents by Inventor Wolf Allers
Wolf Allers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907044Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.Type: GrantFiled: September 13, 2021Date of Patent: February 20, 2024Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers
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Patent number: 11562789Abstract: In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.Type: GrantFiled: December 10, 2020Date of Patent: January 24, 2023Assignee: INFINEON TECHNOLOGIES AGInventors: David Mueller, Wolf Allers, Christian Peters
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Publication number: 20220091914Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state, wherein in the second state, at least one memory cell of the plurality of memory cells is connected to a different evaluation element to which the at least one memory cell is not connected in the first state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state.Type: ApplicationFiled: September 13, 2021Publication date: March 24, 2022Inventors: Jan OTTERSTEDT, Wolf ALLERS
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Publication number: 20210312979Abstract: Read circuitry for a memory cell of a resistive change memory is suggested, wherein a signal of a bit-line that is connected to the memory cell is compared with a reference signal, and wherein the reference signal is determined based on a first dummy circuit that determines a leakage current of memory cells addressed by the bit-line. Also, a corresponding method is provided.Type: ApplicationFiled: March 31, 2021Publication date: October 7, 2021Inventors: Wolf Allers, Jan Otterstedt, Christian Peters
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Publication number: 20210217463Abstract: A position of a memory cell to be accessed within a memory field of a memory device is identified. A region associated with the memory field within which the position is located is identified. A compensation parameter comprising a fixed electric step value for the region is identified. The compensation parameter may be selected from a set of compensation parameters or may be calculated based upon the position of the memory cell. The compensation parameter is applied to an action performed on a line connected to the memory cell during the access of the memory cell.Type: ApplicationFiled: January 13, 2020Publication date: July 15, 2021Inventors: Jan OTTERSTEDT, Wolf ALLERS, Christian PETERS
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Patent number: 11062761Abstract: A position of a memory cell to be accessed within a memory field of a memory device is identified. A region associated with the memory field within which the position is located is identified. A compensation parameter comprising a fixed electric step value for the region is identified. The compensation parameter may be selected from a set of compensation parameters or may be calculated based upon the position of the memory cell. The compensation parameter is applied to an action performed on a line connected to the memory cell during the access of the memory cell.Type: GrantFiled: January 13, 2020Date of Patent: July 13, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Wolf Allers, Christian Peters
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Publication number: 20210174868Abstract: In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.Type: ApplicationFiled: December 10, 2020Publication date: June 10, 2021Inventors: David MUELLER, Wolf Allers, Christian Peters
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Patent number: 9558797Abstract: A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a transistor, precharging a second access point of the transistor to a predetermined voltage, applying a control voltage to a third access point of the transistor, and discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.Type: GrantFiled: April 11, 2016Date of Patent: January 31, 2017Assignee: Infineon Technologies AGInventors: Giacomo Curatolo, Wolf Allers
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Patent number: 9524766Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.Type: GrantFiled: May 18, 2015Date of Patent: December 20, 2016Assignee: Infineon Technologies AGInventors: David Mueller, Wolf Allers, Mihail Jefremow
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Publication number: 20160307608Abstract: A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a transistor, precharging a second access point of the transistor to a predetermined voltage, applying a control voltage to a third access point of the transistor, and discharging the second access point of the transistor to turn on the transistor which causes a current flow through the array cell connected to the transistor.Type: ApplicationFiled: April 11, 2016Publication date: October 20, 2016Inventors: GIACOMO CURATOLO, WOLF ALLERS
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Patent number: 9251864Abstract: The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.Type: GrantFiled: September 6, 2012Date of Patent: February 2, 2016Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Thomas Kern
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Patent number: 9190149Abstract: Embodiments relate to systems and methods including a step of switching between two or more erase operations and/or two or more write operations for erasing of and/or writing to least one memory cell of a nonvolatile memory enabling to select a most suitable erase and/or write operation for a particular erase and/or write operation within the memory.Type: GrantFiled: August 24, 2012Date of Patent: November 17, 2015Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Christian Peters
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Publication number: 20150255136Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.Type: ApplicationFiled: May 18, 2015Publication date: September 10, 2015Inventors: David Mueller, Wolf Allers, Mihail Jefremow
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Patent number: 9076540Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.Type: GrantFiled: August 23, 2012Date of Patent: July 7, 2015Assignee: Infineon Technologies AGInventors: David Mueller, Wolf Allers, Mihail Jefremow
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Patent number: 9070466Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.Type: GrantFiled: September 6, 2012Date of Patent: June 30, 2015Assignee: Infineon Technologies AGInventors: Mihail Jefremow, Wolf Allers, Jan Otterstedt, Christian Peters, Thomas Kern
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Patent number: 9032140Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.Type: GrantFiled: January 28, 2013Date of Patent: May 12, 2015Assignee: Infineon Technologies AGInventors: Wolf Allers, Jan Otterstedt, Mihail Jefremow, Edvin Paparisto, Leonardo Castro
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Patent number: 8837210Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current.Type: GrantFiled: August 23, 2012Date of Patent: September 16, 2014Assignee: Infineon Technologies AGInventors: Mihail Jefremow, Wolf Allers, Jan Otterstedt, Christian Peters, Thomas Kern
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Publication number: 20140215124Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Applicant: Infineon Technologies AGInventors: Wolf Allers, Jan Otterstedt, Mihail Jefremow, Edvin Paparisto, Leonardo Castro
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Patent number: 8670270Abstract: One or more embodiments may be related to a method of operating a phase-change memory element, comprising: providing the phase-change memory element, the phase-change memory element having a first terminal and a second terminal; causing a first current through the memory element from the first terminal to the second terminal; and causing a second current through the memory element from the second terminal to the first terminal, wherein the causing the first current programs the memory element from a first resistance state to a second resistance state and the causing the second current programs the memory element from the first resistance state to the second resistance state.Type: GrantFiled: February 23, 2012Date of Patent: March 11, 2014Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Thomas Nirschl, Christian Peters, Michael Bollu, Wolf Allers, Michael Sommer
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Patent number: 8670277Abstract: A memory includes a memory cell including a first terminal, a second terminal and a channel extending between the first terminal and the second terminal. The memory further includes an energy storage element configured to support a programming of the memory cell, the energy storage element being coupled to the first terminal, an energy supply coupled to the energy storage element, and a controller. The controller is configured to activate the energy supply and to bring the channel of the memory cell into a non-conductive state for energizing the energy storage element, and to subsequently bring the channel of the memory cell into a conductive state for programming the memory cell based on the energy stored in the energy storage element.Type: GrantFiled: July 27, 2011Date of Patent: March 11, 2014Assignee: Infineon Technologies AGInventors: Thomas Nirschl, Jan Otterstedt, Wolf Allers, Dominique Savignac