Abstract: The invention relates to a method and to a circuit for detecting the armature position of an electromagnet. The magnetic voltage is compared with a reference voltage. The reference voltage is used derived from the magnetic voltage by a filtration.

Abstract: Test circuit for testing a synchronous circuit (3) which is clocked with an operating clock signal with a high operating clock frequency, having:

Abstract: Test circuit for testing a synchronous memory circuit Test circuit for testing a synchronous memory circuit (3) having a frequency multiplication circuit (4) which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor in order to produce a high-frequency clock signal for the synchronous memory chip (3) to be tested, a test data generator (16) which produces test data on the basis of data control signals received from the external test unit (2) and outputs them to a data output driver (14) in order to write them to the synchronous memory circuit (3) to be tested, a first signal delay circuit (19) for delaying the test data which are output by the test data generator (16) by an adjustable first delay time, a second signal delay circuit (24) for delaying data which are read out of the synchronous memory circuit (3) to be tested and are received by a data input driver (15) in the test circuit (1) by an adjustable second del

Abstract: Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus, a data comparison circuit, which compares the generated data and the read-out data and, in a manner dependent on the comparison result, transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test unit via an indication signal line, each data line pair of the differential data bus, between the circuit to be tested and the test circuit, having a first data signal line for the transmission of a data signal and a second data signal line for the transmissio

Abstract: Test circuit for testing a circuit (3) which is clocked with a high-frequency clock signal and needs to be tested, where the test circuit (1) has:

Abstract: Address generator for generating addresses for testing an addressable circuit (2), having: at least one base address register (12) for buffer-storing a base address, the base address register (12) in each case being assigned an associated offset register group (13) having a plurality of offset registers for buffer-storing relative address values; a first multiplexer circuit (38), which, in a manner dependent on a base register selection control signal, switches through an address buffer-stored in the base address register (12) to a first input (59) of an addition circuit (60) and to an address bus (3), which is connected to the circuit (2) to be tested; a second multiplexer circuit (17), which, in a manner dependent on the base register selection control signal, through-connects the offset register group (13) associated with the through-connected base address register (12) to a third multiplexer circuit (25), which, in a manner dependent on an offset register selection control signal, through-connects an offs

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

Abstract: Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.

Abstract: A sensor platform for use in sample analysis comprises a substrate (30) of refractive index (n1) and a thin, optically transparent layer (32) of refractive index (n2) on the substrate, (n2) is greater than (n1). The platform incorporates one or multiple corrugated structures in the form of periodic grooves (31), (33), which defines one or more sensing areas each for one or more capture elements. The grooves are so profiled, dimensioned and oriented that when coherent light is incident on the platform it is diffracted into individual beams or diffraction order resulting in reduction of the transmitted beam and an abnormal high reflection of the incident light thereby creates an enhanced evanescent field at the surface of the or each sensing area. The amplitude of this field at the resonant condition is greater by an order of approximately 100 than the field of prior art platforms so that the luminescence intensity created from samples on the platform is also increased by a factor of 100.

Abstract: A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.

Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

Abstract: Disclosed are antibodies which can be used for the manufacture of vaccines for active and/or passive immunization of persons in need of such treatment. The invention also provides for human monoclonal antibodies that are functionally equivalent to the above-mentioned antibodies produced by any one of the cell lines CL1 through CL6 (deposited at the European Collection of Animal Cell Cultures (ECACC) at the PHLS in Porton Down, Salisbury, UK). Also provided are hybridoma and/or CHO cell lines producing any one of the antibodies disclosed and claimed herein, Also provided are mixtures of antibodies of the present invention, as well as methods of using individual antibodies or mixtures thereof for the detection, prevention and/or therapeutical treatment of HIV-1 infections in vitro and in vivo.

Abstract: Described is a moisture-curing sealing and bonding compound made from completely synthetic polymers, the compound containing, to improve its non-sag properties, a triglyceride, either as the sole non-sag agent or in addition to prior art agents. The triglyceride should have a melting point over 40.degree. C., preferably over 50.degree. C., and be derived from saturated fatty acids with 8 to 26 C-atoms. Even without using thixotropic agents, compounds can be obtained which do not sag at temperatures over 40.degree. C. Such joint sealants can be used to fill joints more than 35 mm wide without sagging.

Abstract: Disclosed are antibodies which can be used for the manufacture of vaccines for active and/or passive immunization of persons in need of such treatment. The invention also provides for human monoclonal antibodies that are functionally equivalent to the above-mentioned antibodies produced by any one of the cell lines CL1 through CL6 (deposited at the European Collection of Animal Cell Cultures (ECACC) at the PHLS in Porton Down, Salisbury, UK). Also provided are hybridoma and/or CHO cell lines producing any one of the antibodies disclosed and claimed herein. Also provided are mixtures of antibodies of the present invention, as well as methods of using individual antibodies or mixtures thereof for the detection, prevention and/or therapeutical treatment of HIV-1 infections in vitro and in vivo.

Abstract: The invention relates to an electronic teaching, accompaniment and practice music apparatus which is independent of a played musical instrument. The apparatus includes devices for digital sound production, tempo setting, accompaniment, operation and input of digital note data, which are connected by means of a control unit, which is connected with an electro-acoustical device for acoustical reproduction of the note sequences corresponding to the input piece of music via a digital-analog converter. There is an optical display device which is connected with a piano keyboard or a guitar fingerboard or represents these, for optical display of the note sequences played.

Abstract: Moisture-hardening joint sealing compositions based on polyurethane prepolymers, swellable polymer powders, plasticizers and other auxiliaries have increased stability in storage when they contain C.sub.8 -C.sub.20 olefins as stabilizers.