Abstract: The invention relates to a method for controlling digital-to-analog converters (DAC), the method comprising: providing a plurality of digital-to-analog converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analog RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analog RF data signals provided at respective output terminals of each DAC comprise a pre-defined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals. The invention further relates to a converter arrangement RF transmit circuit arrangement.

Abstract: A box-frame housing for the installation of electronic modules has frame elements and side walls and provides a subdivision into sub-regions, which are limited by dividing walls. The frame elements and the side walls and the dividing walls provide at least one recess and/or at least one edge projection. A projection engages in a recess and both are connected to one another by welding.

Abstract: The invention relates to a method for controlling digital-to-analogue converters (DAC), the method comprising: providing a plurality of digital-to-analogue converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analogue RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analogue RF data signals provided at respective output terminals of each DAC comprise a pre-defined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals. The invention further relates to a converter arrangement RF transmit circuit arrangement.

Abstract: A box-frame housing for the installation of electronic modules has frame elements and side walls and provides a subdivision into sub-regions, which are limited by dividing walls. The frame elements and the side walls and dividing walls provide at least one recess and/or at least one edge projection. A projection engages in a recess and both are connected to one another by welding.

Abstract: A box-frame housing for the installation of electronic modules has frame elements and side walls and provides a subdivision into sub-regions, which are limited by dividing walls. The frame elements and the side walls and the dividing walls provide at least one recess and/or at least one edge projection. A projection engages in a recess and both are connected to one another by welding.

Abstract: A box-frame housing for the installation of electronic modules has frame elements and side walls and provides a subdivision into sub-regions, which are limited by dividing walls. The frame elements and the side walls and dividing walls provide at least one recess and/or at least one edge projection. A projection engages in a recess and both are connected to one another by welding.

Abstract: The invention relates to a signal generator for a DSSS or CDMA signal, comprising several spread sequence memories and a digital signal processor which pre-calculates the spread sequence in an initialization phase and deposits the same in the spread sequence memory, and which supplies data symbols to an image memory in an operating phase. Each image memory contains an image table by means of which the bits of the current data symbols and at least one current bit of the spread sequence, which is sequentially read from every spread sequence memory, is imaged in at least one output value.

Abstract: To achieve a synchronous output of analog signals generated in two or more digital-to-analog (DAC) converters, an adjustable, digital delay device, of which the delay time is adjustable dependent upon the cross-correlation determined between the analog output signals of the digital-to-analog converters, is provided upstream of at least one of the fifo memories provided for the signal transfer in order to delay the digital signal.

Abstract: To achieve a synchronous output of analog signals generated in two or more digital-to-analog (DAC) converters, an adjustable, digital delay device, of which the delay time is adjustable dependent upon the cross-correlation determined between the analog output signals of the digital-to-analog converters, is provided upstream of at least one of the fifo memories provided for the signal transfer in order to delay the digital signal.

Abstract: A signal generator comprises at least one first base band unit and a second base band unit, generating a digital base band signal. At least one first frequency offset unit, connected to the first base band unit, which adds the output signal form the second base band unit and the output signal from the frequency offset unit and an I/Q modulator, in series with the addition unit are provided.

Abstract: A signal generator comprises at least one first base band unit and a second base band unit, generating a digital base band signal. At least one first frequency offset unit, connected to the first base band unit, which adds the output signal form the second base band unit and the output signal from the frequency offset unit and an I/Q modulator, in series with the addition unit are provided.

Abstract: The invention relates to a signal generator (1) for a DSSS or CDMA signal, comprising several spread sequence memories (151, 161; 15N, 16N) and a digital signal processor (10) which pre-calculates the spread sequence in an initialization phase and deposits the same in the spread sequence memory (151, 161; 15N, 16N), and which supplies data symbols to an image memory (141; 14N) in an operating phase. Each image memory (141; 14N) contains an image table by means of which the bits (DI,DQ) of the current data symbols and at least one current bit of the spread sequence, which is sequentially read from every spread sequence memory, is imaged in at least one output value.

Abstract: For the continuous and interruption-free readout of a data sequence predetermined by a predetermined address sequence from a memory that is constructed of dynamic memory components (DRAM or SDRAM) and that is divided into a number of separately addressable memory banks, the control circuit controlling the readout of the data sequence from the memory cells is operated, and the distribution of the data in the memory cells of the banks is selected, such that another bank is respectively refreshed during the readout of data from one of the banks. The memory contains at least three memory banks and the sequence of the bank addresses is always selected such that, given access to a bank, at least the access onto the preceding bank did not exhibit the same bank address.