Patents by Inventor Wolfgang Penth
Wolfgang Penth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11043938Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scannable storage element has both a scannable storage element output and a set of flip-flops. A memory array is connected with the scannable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: GrantFiled: December 19, 2019Date of Patent: June 22, 2021Assignee: International Business Machines CorporationInventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Patent number: 10984843Abstract: A memory cell arrangement for Random Access Memory (RAM) including one or more RAM cell groups. The RAM cell groups having two or more local bit-lines sharing a Global Bit-Line (GBL), a pre-charging circuit connected to the GBL, a multiplexer connected to multiple GBLs and configured to shift an output of a first GBL from a first bit to a second bit at least in part according to a value of a fuse bit register associated with a second GBL, and at least one pre-charge enabling circuit controlled by a combination of a pre-charge input value applied to all GBLs of the memory cell arrangement and a pre-charge enable signal for the GBL.Type: GrantFiled: March 1, 2019Date of Patent: April 20, 2021Assignee: International Business Machines CorporationInventors: Martin Bernhard Schmidt, Harry Barowski, Simon Brandl, Wolfgang Penth
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Publication number: 20200279593Abstract: A memory cell arrangement for Random Access Memory (RAM) including one or more RAM cell groups. The RAM cell groups having two or more local bit-lines sharing a Global Bit-Line (GBL), a pre-charging circuit connected to the GBL, a multiplexer connected to multiple GBLs and configured to shift an output of a first GBL from a first bit to a second bit at least in part according to a value of a fuse bit register associated with a second GBL, and at least one pre-charge enabling circuit controlled by a combination of a pre-charge input value applied to all GBLs of the memory cell arrangement and a pre-charge enable signal for the GBL.Type: ApplicationFiled: March 1, 2019Publication date: September 3, 2020Inventors: Martin Bernhard Schmidt, Harry Barowski, Simon Brandl, Wolfgang Penth
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Publication number: 20200127649Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scannable storage element has both a scannable storage element output and a set of flip-flops. A memory array is connected with the scannable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Patent number: 10587248Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: GrantFiled: January 24, 2017Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Patent number: 10367481Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: GrantFiled: February 20, 2018Date of Patent: July 30, 2019Assignee: International Business Machines CorporationInventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Publication number: 20180212595Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: ApplicationFiled: February 20, 2018Publication date: July 26, 2018Inventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Publication number: 20180212594Abstract: Disclosed aspects relate to a digital logic circuit. A clock generation circuitry has both a clock generation circuitry output and an inverter circuit to generate a derivative clock signal feature by inverting an array clock signal feature. A scanable storage element has both a scanable storage element output and a set of flip-flops. A memory array is connected with the scanable storage element output and the array clock signal feature. The digital logic circuit is configured to avoid a race violation.Type: ApplicationFiled: January 24, 2017Publication date: July 26, 2018Inventors: Harry Barowski, Werner Juchmes, Michael B. Kugel, Wolfgang Penth
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Patent number: 9837142Abstract: A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.Type: GrantFiled: July 12, 2016Date of Patent: December 5, 2017Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Michael B. Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille, Tobias Werner
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Patent number: 9805823Abstract: A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.Type: GrantFiled: January 25, 2017Date of Patent: October 31, 2017Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Michael B. Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille, Tobias Werner
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Patent number: 9715944Abstract: A memory array includes m·(n+1) memory cells, wherein n and m are natural numbers greater than zero. Each of the plurality of memory cells is connected to one of (n+1) bitlines and one of m wordlines. The memory array further includes n outputs configured for reading a content of the memory array. The memory array further includes n output switches, wherein an i-th output switch is configured for selectively connecting, in response to a switching signal, either an i-th bitline or an (i+1)-th bitline to an i-th output, and wherein i is a natural number and 0?i?n?1. The memory array further includes an (n+1)-th output switch, wherein the (n+1)-th output switch is configured for selectively connecting, in response to the switching signal, either the (n+1)-th bitline or a defined potential to an (n+1)-th output.Type: GrantFiled: June 15, 2016Date of Patent: July 25, 2017Assignee: International Business Machines CorporationInventors: Lior Binyamini, Stefan Payer, Wolfgang Penth, Ido Rozenberg
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Patent number: 9704567Abstract: A memory cell that is readable through a bit line and addressable through a word line can be stressed using a method that includes addressing the memory cell, through the word line, for an addressing time. The memory cell can be stressed by applying a stress voltage to the bit line for a stress voltage time that overlaps with the addressing time for a stress time ?t. A method for testing a memory cell can include writing a data value into the memory cell, stressing the memory cell, reading a stored value from the memory cell and determining whether the stored value corresponds to the data value. A testable memory array can include at least one memory cell that is addressable through a word line and readable through a bit line and a stress circuit for applying a stress voltage to the bit line.Type: GrantFiled: July 12, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Michael B. Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille
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Patent number: 9437285Abstract: An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address decoders. The first address decoder comprises a first latch, the second address decoder a second latch. First and second address data paths provide first and second address data to the at least two address decoders. The first latch is electrically conductive connected to the first data path and the second latch is electrically conductive connected to the second data path. The first latch is further electrically conductive connectable to the second data path via a first multiplexer. The first multiplexer and the at least two latches are configured to be selectively operated in a first write mode for a write access or in a read mode for a read access to the memory array.Type: GrantFiled: March 15, 2016Date of Patent: September 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harry Barowski, Silke Penth, Wolfgang Penth, Tobias Werner
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Patent number: 9406375Abstract: An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address decoders. The first address decoder comprises a first latch, the second address decoder a second latch. First and second address data paths provide first and second address data to the at least two address decoders. The first latch is electrically conductive connected to the first data path and the second latch is electrically conductive connected to the second data path. The first latch is further electrically conductive connectable to the second data path via a first multiplexer. The first multiplexer and the at least two latches are configured to be selectively operated in a first write mode for a write access or in a read mode for a read access to the memory array.Type: GrantFiled: December 4, 2015Date of Patent: August 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harry Barowski, Silke Penth, Wolfgang Penth, Tobias Werner
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Patent number: 8493812Abstract: A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost phase to generate a boost voltage. In this case, the boost voltage is applied to a driver circuit of the device only during the boost phase and at least one of the first and second voltages is adjustable, thereby making the boost voltage adjustable.Type: GrantFiled: October 28, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Osama Dengler, Alexander Fritsch, Wolfgang Penth, Juergen Pille
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Patent number: 8422313Abstract: In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.Type: GrantFiled: October 28, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Stefan Buettner, David A. Hrusecky, Werner Juchmes, Wolfgang Penth, Rolf Sautter
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Publication number: 20120155188Abstract: In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.Type: ApplicationFiled: October 28, 2011Publication date: June 21, 2012Applicant: International Business Machines CorporationInventors: Stefan Buettner, David A. Hrusecky, Werner Juchmes, Wolfgang Penth, Rolf Sautter
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Publication number: 20120106237Abstract: A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost phase to generate a boost voltage. In this case, the boost voltage is applied to a driver circuit of the device only during the boost phase and at least one of the first and second voltages is adjustable, thereby making the boost voltage adjustable.Type: ApplicationFiled: October 28, 2010Publication date: May 3, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: OSAMA DENGLER, ALEXANDER FRITSCH, WOLFGANG PENTH, JUERGEN PILLE
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Patent number: 7495949Abstract: An asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory including such memory cells and to a method of operating such a memory.Type: GrantFiled: January 31, 2007Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Stefan Buettner, Torsten Mahnke, Wolfgang Penth, Otto Wagner
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Publication number: 20070189061Abstract: Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory The invention relates to an asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (b1t, b1c) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory comprising such memory cells and to a method of operating such a memory.Type: ApplicationFiled: January 31, 2007Publication date: August 16, 2007Inventors: Stefan Buettner, Torsten Mahnke, Wolfgang Penth, Otto Wagner