Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Abstract: The invention relates to compositions for preparing a beverage, the compositions comprise a microorganism and/or an enzyme capable of hydrolysing chlorogenic acids of a coffee extract to phenolic acids. When a beverage prepared with the compositions of the invention is consumed chlorogenic acids present in coffee extract is hydrolysed to improve antioxidant and/or anti-inflammatory properties compared to a similar conventional beverage.

Abstract: The invention relates to compositions for preparing a beverage, the compositions comprise a microorganism and/or an enzyme capable of hydrolysing chlorogenic acids of a coffee extract to phenolic acids. When a beverage prepared with the compositions of the invention is consumed chlorogenic acids present in coffee extract is hydrolysed to improve antioxidant and/or anti-inflammatory properties compared to a similar conventional beverage.

Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Abstract: The present invention relates generally to the field of food and drinks. In particular, for example, a composition is provided that allows to provide tartaric and/or caffeic acid to a subject. One embodiment of the present invention is a composition comprising an ingredient containing caftaric acid and/or derivatives thereof, and a lactic acid bacterium capable of hydrolysing caftaric acid and/or derivatives thereof to generate tartaric and/or caffeic acid.

Abstract: The present invention relates generally to the field of food and drinks. In particular, for example, a composition is provided that allows to provide tartaric and/or caffeic acid to a subject. One embodiment of the present invention is a composition comprising an ingredient containing chicoric acid and/or derivatives thereof, and a lactic acid bacterium capable of hydrolysing chicoric acid and/or derivatives thereof to generate tartaric and/or caffeic acid.

Abstract: The present invention relates to a method of producing a coffee extract with antioxidant and anti-inflammatory properties and uses of the extract of the invention. The coffee extract comprises caffeic acid and/or ferulic acid and can be produced by hydrolysing chlorogenic acids present in coffee extract, e.g. with a microorganism or an enzyme. The coffee extract of the invention may e.g. be used as an ingredient of a food or beverage product.

Abstract: The present invention relates to uses of decarboxylated phenolic acid derived from chlorogenic acid of coffee as well as products comprising decarboxylated phenolic acid derived from chlorogenic acid of coffee, especially a coffee extract, and methods of producing such products. Coffee comprises chlorogenic acids, according to the invention these chlorogenic acids can be transformed into decarboxylated phenolic acids. The resulting decarboxylated phenolic acids have antioxidant and/or anti-inflammatory properties and can be used as ingredients in food and beverage products and to treat certain health conditions.

Abstract: The invention relates to compositions for preparing a beverage, the compositions comprise a microorganism and/or an enzyme capable of hydrolysing chlorogenic acids of a coffee extract to phenolic acids. When a beverage prepared with the compositions of the invention is consumed chlorogenic acids present in coffee extract is hydrolysed to improve antioxidant and/or anti-inflammatory properties compared to a similar conventional beverage.

Abstract: The apparatus has a multiplicity of control modules which are assigned to a multiplicity of processing modules for driving purposes. These separate control modules are driven by a superordinate controller and are synchronized by a common synchronization unit on the basis of, by way of example, handshake lines and semaphores. The effect achieved by such an apparatus is that the transmission bandwidth between an external instruction memory and the large-scale integrated system can be reduced, and the total power loss can be lowered by intermittently disconnecting processing modules which are currently not needed. Furthermore, such an architecture supports the separate development of control programs for the individual control modules.

Abstract: The subject matter of the application essentially relates to a matrix array of processor units, each processor unit having, in addition to an arithmetic logic unit and a result register bank, a further arithmetic logic unit, a multiplier/adder unit, a storage unit of a distributed screen section buffer and a local general purpose memory. The processor is distinguished by a high processing speed in conjunction with a small chip area and enables real-time processing even in the case of computation-intensive image processing methods such as 2D convolution, Gabor transformation, Gaussian or Laplacian pyramids, block matching, DCT or MPEG2.

Abstract: The dynamic semiconductor memory is divided into word line blocks and bit line blocks, word line blocks consisting of a plurality of bit line blocks, which includes for each bit line block a local SAN driver (LTN) and an decelerator circuit for driving the read amplifiers (LV1 . . . LVi) associated with the respective bit line block, and the accelerator circuits of which can be driven in such a way that, to achieve a low total peak current, only the accelerator circuit belonging to the bit line block is active whose bit lines are switched through to IO lines (IO, ION). The accelerator circuit consists, for example, of only one driver transistor (NT.sub.n+1) in each case.