Patents by Inventor Wolfgang Walthes
Wolfgang Walthes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10862428Abstract: An envelope tracking system for controlling a power amplifier supply voltage includes envelope circuitry and a feed forward digital to analog converter (DAC) circuitry. The envelope circuitry is configured to generate a target envelope signal based on a selected power amplifier supply voltage. The feed forward DAC circuitry includes a voltage source circuitry and a selector circuitry. The voltage source circuitry is configured to generate a plurality of voltages. The selector circuitry is configured to select one of the plurality of voltages based at least on the target envelope signal. The feed forward DAC circuitry is configured to provide the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal.Type: GrantFiled: September 25, 2018Date of Patent: December 8, 2020Assignee: Apple Inc.Inventors: Stephan Henzler, Andreas Menkhoff, Thomas Eichler, Wolfgang Walthes, Alexander Belitzer, Yifan Wang
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Publication number: 20190036486Abstract: An envelope tracking system for controlling a power amplifier supply voltage includes envelope circuitry and a feed forward digital to analog converter (DAC) circuitry. The envelope circuitry is configured to generate a target envelope signal based on a selected power amplifier supply voltage. The feed forward DAC circuitry includes a voltage source circuitry and a selector circuitry. The voltage source circuitry is configured to generate a plurality of voltages. The selector circuitry is configured to select one of the plurality of voltages based at least on the target envelope signal. The feed forward DAC circuitry is configured to provide the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal.Type: ApplicationFiled: September 25, 2018Publication date: January 31, 2019Inventors: Stephan Henzler, Andreas Menkhoff, Thomas Eichler, Wolfgang Walthes, Alexander Belitzer, Yifan Wang
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Patent number: 10090808Abstract: An envelope tracking system for controlling a power amplifier supply voltage includes envelope circuitry and a feed forward digital to analog converter (DAC) circuitry. The envelope circuitry is configured to generate a target envelope signal based on a selected power amplifier supply voltage. The feed forward DAC circuitry includes a voltage source circuitry and a selector circuitry. The voltage source circuitry is configured to generate a plurality of voltages. The selector circuitry is configured to select one of the plurality of voltages based at least on the target envelope signal. The feed forward DAC circuitry is configured to provide the selected voltage to a supply voltage input of a power amplifier that amplifies a radio frequency (RF) transmit signal.Type: GrantFiled: March 30, 2017Date of Patent: October 2, 2018Assignee: Intel IP CorporationInventors: Stephan Henzler, Andreas Menkhoff, Thomas Eichler, Wolfgang Walthes, Alexander Belitzer, Yifan Wang
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Patent number: 8271827Abstract: A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.Type: GrantFiled: December 10, 2007Date of Patent: September 18, 2012Assignee: QimondaInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Patent number: 8144755Abstract: The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.Type: GrantFiled: November 29, 2007Date of Patent: March 27, 2012Inventors: Michael Bruennert, Christoph Bilger, Peter Gregorius, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Patent number: 8120958Abstract: The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.Type: GrantFiled: December 24, 2007Date of Patent: February 21, 2012Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Patent number: 8015438Abstract: The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.Type: GrantFiled: November 29, 2007Date of Patent: September 6, 2011Assignee: Qimonda AGInventors: Michael Bruennert, Christoph Bilger, Peter Gregorius, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Patent number: 7928525Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.Type: GrantFiled: April 25, 2008Date of Patent: April 19, 2011Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Patent number: 7920433Abstract: Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.Type: GrantFiled: January 9, 2008Date of Patent: April 5, 2011Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20110034045Abstract: Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device.Type: ApplicationFiled: August 6, 2009Publication date: February 10, 2011Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20090287957Abstract: A memory control unit for controlling a memory module comprising a plurality of memory cells, said memory control unit comprising means for detecting failure of at least one memory cell, means for deactivating said at least one defective memory cell, means for assigning the address of said at least one defective memory cell to at least one replacement memory cell, first tracking means for tracking the remaining replacement memory cells and masking means to hide the address of a defective memory cell to prevent further usage of this address instead of assigning said address to a replacement memory cell.Type: ApplicationFiled: May 16, 2008Publication date: November 19, 2009Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler
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Publication number: 20090267084Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.Type: ApplicationFiled: April 25, 2008Publication date: October 29, 2009Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20090267678Abstract: An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed.Type: ApplicationFiled: April 25, 2008Publication date: October 29, 2009Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20090190432Abstract: A DRAM chip with a data I/O-interface of an access width equal to a page size.Type: ApplicationFiled: January 28, 2008Publication date: July 30, 2009Inventors: Christoph BILGER, Peter GREGORIUS, Michael BRUENNERT, Maurizio SKERJI, Wolfgang WALTHES, Johannes STECKER, Hermann RUCKERBAUER, Dirk SCHEIDELER, Roland BARTH
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Publication number: 20090175100Abstract: Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.Type: ApplicationFiled: January 9, 2008Publication date: July 9, 2009Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20090175115Abstract: Embodiments relates to a memory device, comprising a plurality of memory cells, said memory cells being addressable by a plurality of addresses, an interface for reading and/or writing data from a host system to said memory device, said interface comprising at least an address bus and a clock signal line, said address bus being configured to transmit a first part of an address at the leading edge of said clock signal and a second part of an address at the trailing edge of said clock signal.Type: ApplicationFiled: January 9, 2008Publication date: July 9, 2009Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler
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Publication number: 20090161401Abstract: The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.Type: ApplicationFiled: December 24, 2007Publication date: June 25, 2009Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20090150710Abstract: A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20090141843Abstract: The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Applicant: QIMONDA AGInventors: Michael Bruennert, Chistoph Bilger, Peter Gregorius, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
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Publication number: 20090144583Abstract: The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Applicant: QIMONDA AGInventors: Michael Bruennert, Chistoph Bilger, Peter Gregorius, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth