Abstract: A high voltage connector for a vehicle may include a male connector having a truncated conical protuberance-shaped first terminal, and a female connector having a second terminal provided with a truncated conical coupling groove corresponding to the first terminal, wherein an electrical connection between the male connector and the female connector is accomplished as the first terminal is inserted into the coupling groove of the second terminal. When the first terminal and the second terminal are coupled to each other, elastic deformation may be induced which may provide a holding force between the first and second terminals using elastic stress, resulting in improved stability of a high voltage power supply.

Abstract: A semiconductor device includes an active pattern extending in a first direction on a substrate, a gate structure on the active pattern and having a gate electrode extending in a second direction intersecting the active pattern, and a gate capping pattern on the gate electrode, the gate capping pattern including a gate capping liner defining a gate capping recess, the gate capping liner having a horizontal portion along an upper surface of the gate electrode, and a vertical portion extending from the horizontal portion in a third direction intersecting the first and second directions, and a gate capping filling film on the gate capping liner and filling the gate capping recess, an epitaxial pattern on the active pattern and adjacent the gate structure, a gate contact on and connected to the gate electrode, and an active contact on and connected to the epitaxial pattern.

Abstract: An integrated circuit device includes a static random access memory (SRAM) array, and the SRAM array includes first to fourth active fins extending parallel to each other in a first direction, a first gate line overlapping the second to fourth active fins, a second gate line spaced apart from the first gate line in the first direction and overlapping the first to third active fins, a third gate line spaced apart from the first gate line in the first direction and overlapping the fourth active fin, a fourth gate line spaced apart from the second gate line in the first direction and overlapping the first active fin, a first field isolation layer contacting one end of the second active fin, and a second field isolation layer contacting one end of the third active fin. The first to fourth gate lines extend in a second direction intersecting the first direction.

Abstract: An integrated circuit device includes a static random access memory (SRAM) array, and the SRAM array includes first to fourth active fins extending parallel to each other in a first direction, a first gate line overlapping the second to fourth active fins, a second gate line spaced apart from the first gate line in the first direction and overlapping the first to third active fins, a third gate line spaced apart from the first gate line in the first direction and overlapping the fourth active fin, a fourth gate line spaced apart from the second gate line in the first direction and overlapping the first active fin, a first field isolation layer contacting one end of the second active fin, and a second field isolation layer contacting one end of the third active fin. The first to fourth gate lines extend in a second direction intersecting the first direction.

Abstract: A coil assembly and a magnetic resonance imaging (MRI) apparatus including the same are disclosed. After completion of inspection or repair of the coil assembly, the coil assembly is easily coupled to the Mill apparatus. The coil assembly is configured to interact with a magnetic field generated from a MM apparatus and includes a first case configured to be bendable, a second case configured to be bendable and detachably coupled to the first case, and a printed circuit board substrate disposed between the first case and the second case.

Abstract: Disclosed is a construction machine with a floating function for performing soil preparation or the like for flattening the ground or the like using a dozer blade.

Abstract: Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.

Abstract: A non-volatile memory device can include a plurality of parallel active regions that are defined by a plurality of device isolation layers formed on a semiconductor substrate, where each of the plurality of parallel active regions extends in a first direction and has a top surface and sidewalls. A plurality of parallel word lines can extend in a second direction and cross over the plurality of parallel active regions at intersecting locations. A plurality of charge storage layers can be disposed at the intersecting locations between the plurality of parallel active regions and the plurality of parallel word lines. Each of the plurality of charge storage layers at the intersecting locations can have a first side and a second side that is parallel to the second direction and can have a first length, a third side and a fourth side that are parallel to the first direction and can have a second length, where the first length is less than the second length.

Abstract: An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction.

Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

Abstract: Methods of fabricating semiconductor devices including providing a substrate having a channel region defined therein; forming an insulation layer on the substrate; forming a gate trench for forming a gate electrode having a sidewall portion, a bottom portion and an edge portion between the sidewall portion and the bottom portion on the insulation layer, the gate electrode trench overlapping the channel region; and forming a gate electrode in the gate electrode trench. Forming the gate electrode includes forming a first metal layer pattern in the gate electrode trench and forming a second metal layer pattern on the first metal layer pattern.

Abstract: A phase-change random-access memory (PRAM) device includes a chalcogenide element, the chalcogenide element comprising a material which can assume a crystalline state or an amorphous state upon application of a heating current. A first contact is connected to a first region of the chalcogenide element and has a first cross-sectional area. A second contact is connected to a second region of the chalcogenide element and having a second cross-sectional area. A first programmable volume of the chalcogenide material is defined in the first region of the chalcogenide element, a state of the first programmable volume being programmable according to a resistance associated with the first contact. A second programmable volume of the chalcogenide material is defined in the second region of the chalcogenide element, a state of the second programmable volume being programmable according to a second resistance associated with the second contact.

Abstract: In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.

Abstract: A non-volatile memory device can include a plurality of parallel active regions that are defined by a plurality of device isolation layers formed on a semiconductor substrate, where each of the plurality of parallel active regions extends in a first direction and has a top surface and sidewalls. A plurality of parallel word lines can extend in a second direction and cross over the plurality of parallel active regions at intersecting locations. A plurality of charge storage layers can be disposed at the intersecting locations between the plurality of parallel active regions and the plurality of parallel word lines. Each of the plurality of charge storage layers at the intersecting locations can have a first side and a second side that is parallel to the second direction and can have a first length, a third side and a fourth side that are parallel to the first direction and can have a second length, where the first length is less than the second length.

Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

Abstract: Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.

Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

Abstract: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.

Abstract: An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction.

Abstract: A phase-change random-access memory (PRAM) device includes a chalcogenide element, the chalcogenide element comprising a material which can assume a crystalline state or an amorphous state upon application of a heating current. A first contact is connected to a first region of the chalcogenide element and has a first cross-sectional area. A second contact is connected to a second region of the chalcogenide element and having a second cross-sectional area. A first programmable volume of the chalcogenide material is defined in the first region of the chalcogenide element, a state of the first programmable volume being programmable according to a resistance associated with the first contact. A second programmable volume of the chalcogenide material is defined in the second region of the chalcogenide element, a state of the second programmable volume being programmable according to a second resistance associated with the second contact.