Abstract: A memory device and an electronic device is provided. The memory device may include a memory module including a module board and a memory connector located on one side of the module board, a first enclosure placed above the memory module and a second enclosure placed below the memory module, wherein the first enclosure includes a first main cover which covers upper faces of the module board and the memory connector, at least one clamping hole which penetrates the main cover at a position overlapping the memory connector, an inter-device fastening pillar protruding downward from a lower face of the first main cover, and a coupling hole which is located inside the inter-device fastening pillar on a plane and penetrates the inter-device fastening pillar and the main cover.

Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on the body and connected to the internal electrode layer. At least one hole is formed in the internal electrode layer, and a region, containing at least one selected from the group consisting of indium (In) and tin (Sn), is disposed in the hole. A method of manufacturing a capacitor component includes forming a dielectric green sheet, forming a conductive thin film, including a first conductive material and a second conductive material, on the dielectric green sheet, and sintering the conductive thin film to form an internal electrode layer. The internal electrode layer includes the first conductive material, and a region, including the second conductive material, is formed in the internal electrode layer.

Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.

Abstract: A memory device and an electronic device is provided. The memory device may include a memory module including a module board and a memory connector located on one side of the module board, a first enclosure placed above the memory module and a second enclosure placed below the memory module, wherein the first enclosure includes a first main cover which covers upper faces of the module board and the memory connector, at least one clamping hole which penetrates the main cover at a position overlapping the memory connector, an inter-device fastening pillar protruding downward from a lower face of the first main cover, and a coupling hole which is located inside the inter-device fastening pillar on a plane and penetrates the inter-device fastening pillar and the main cover.

Abstract: The present invention relates to a composition for forming a composite polymer film, a method for preparing the composition for forming a composite polymer film, a composite polymer film and a method for preparing the composite polymer film. The composition for forming a composite polymer film comprises: a fluorine-based polymer solution comprising a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the fluorine-based polymer solution. The method for preparing the composition for forming a composite polymer film comprises the steps of: preparing a fluorine-based polymer solution comprising a fluorine-based polymer; and dispersing polyvinylidene fluoride nanoparticles in the fluorine-based polymer solution. The composite polymer film comprises: a polymer matrix formed from a fluorine-based polymer; and polyvinylidene fluoride nanoparticles dispersed in the polymer matrix.

Abstract: A gene amplification chip includes a chamber layer, a cover layer, a bottom layer, an inlet, and an outlet. The chamber layer has a first passage and through holes which are formed on one side of the first passage. The cover layer is disposed on one side of the chamber layer and has a cover channel formed to communicate with the first passage and the through holes, wherein the cover channel, the first passage and the through holes allow passage of liquids in a divided manner. The bottom layer is disposed on another side of the chamber layer and has a bottom channel formed to communicate with the first passage and the through holes. The inlet is formed in the cover layer and communicates with the cover channel. The outlet communicates with any one of the cover channel and the bottom channel.

Abstract: An object of the present invention is to provide a heat exchanger that is structurally coupled to an endplate without a process of welding a connection member. To achieve the above-mentioned object, a heat exchanger according to the present invention may include a plurality of main plates each including a through-hole through which a heat exchange medium flows, and an outer wall formed at a periphery thereof, the plurality of main plates being stacked to constitute a heat exchanger core having a flow path formed therein, an endplate being in surface contact with the main plate disposed at an outermost side of the heat exchanger core, the endplate having one or more connection holes, and a connection member configured to be connected to an external component and at least partially inserted into the connection hole.

Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

Abstract: A method according to some embodiments of the invention includes sequentially forming first and second conductive layers, patterning the second conductive layer to form second conductive patterns, and forming a mask pattern connecting the second conductive patterns. Using the mask pattern and the second conductive patterns as an etching mask, the first conductive layer is etched to form a first conductive pattern electrically connecting the second conductive patterns. Before the second conductive layer is formed, a gate interlayer insulating layer including at least two openings exposing a top surface of the first conductive layer may be formed. The second conductive patterns are in contact with top surfaces of the first conductive pattern. During formation of the second conductive patterns, a dummy pattern may be formed on the gate interlayer insulating layer and spaced apart from the second conductive patterns.

Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

Abstract: A non-volatile memory cell array having second floating gates with a narrow width, a large height, and slanted side walls. Critical dimension errors due to photolithographic and etching processes are decreased. The difference in the coupling ratio between the memory cells is low thereby improving speed during programming and/or erasing. A second floating gate having a narrower critical dimension than a second floating gate obtained using a photolithographic process may be designed, thereby forming a highly integrated non-volatile memory cell array.

Abstract: Provided are a non-volatile flash memory device and a method of making the non-volatile flash memory device. A common source line is formed simultaneously with the formation of stacked transistors. The common source line is formed of the same material layer as floating gate pattern. The common source region and a scribe line region are simultaneously formed thorough the same photolithography process in a semiconductor substrate. Additionally, the common source line and butted contact are patterned simultaneously through the same photolithography process. Accordingly, the common source line process can be advantageously completed with very low cost and simplicity.

Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

Abstract: A non-volatile memory cell array having second floating gates with a narrow width, a large height, and slanted side walls. Critical dimension errors due to photolithographic and etching processes are decreased. The difference in the coupling ratio between the memory cells is low thereby improving speed during programming and/or erasing. A second floating gate having a narrower critical dimension than a second floating gate obtained using a photolithographic process may be designed, thereby forming a highly integrated non-volatile memory cell array.

Abstract: Provided are a non-volatile flash memory device and a method of making the non-volatile flash memory device. A common source line is formed simultaneously with the formation of stacked transistors. The common source line is formed of the same material layer as floating gate pattern. The common source region and a scribe line region are simultaneously formed thorough the same photolithography process in a semiconductor substrate. Additionally, the common source line and butted contact are patterned simultaneously through the same photolithography process. Accordingly, the common source line process can be advantageously completed with very low cost and simplicity.

Abstract: Provided are a non-volatile flash memory device and a method of making the non-volatile flash memory device. A common source line is formed simultaneously with the formation of stacked transistors. The common source line is formed of the same material layer as floating gate pattern. The common source region and a scribe line region are simultaneously formed thorough the same photolithography process in a semiconductor substrate. Additionally, the common source line and butted contact are patterned simultaneously through the same photolithography process. Accordingly, the common source line process can be advantageously completed with very low cost and simplicity.