Abstract: A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS transistor has a first terminal connected to a high power source, and a gate to which a control voltage is applied and which has a plurality of fingers. The low finger NMOS transistor has a first terminal connected to a low power source, a gate to which the control voltage is applied and which has a plurality of fingers, and a second terminal connected to a second terminal of the PMOS transistor. The number of the fingers of the gate of the NMOS transistor is smaller than the number of fingers of the gate of the PMOS transistor and the length of each of the fingers of the NMOS transistor is greater than the length of each of the fingers of the PMOS transistor.

Abstract: A semiconductor device having an electro static discharge (ESD) protection circuit includes an input/output pad configured to receive a voltage higher than an operating voltage of the semiconductor device and an ESD (electro static discharge) protection circuit configured to protect an internal circuit of the semiconductor device from ESD when ESD occurs at the input/output pad. The ESD protection circuit may include a protection circuit configured to flow the ESD current into an operating voltage line and/or a ground voltage line, an ESD detection circuit configured to detect the ESD current flowing in the operating voltage line, and a control circuit configured to cause the protection circuit to be coupled to, or isolated from, the ground voltage line in response to an output signal of the ESD detection circuit.

Abstract: An electrostatic discharge (ESD) protection circuit has a low trigger voltage. The ESD protection circuit is coupled between two rails. The ESD protection circuit includes a connection load and a second transistor. The connection load turns on a first transistor when an ESD event occurs, and the second transistor generates a current due to an avalanche breakdown. A latch-up current is generated due to the avalanche breakdown.

Abstract: A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS transistor has a first terminal connected to a high power source, and a gate to which a control voltage is applied and which has a plurality of fingers. The low finger NMOS transistor has a first terminal connected to a low power source, a gate to which the control voltage is applied and which has a plurality of fingers, and a second terminal connected to a second terminal of the PMOS transistor. The number of the fingers of the gate of the NMOS transistor is smaller than the number of fingers of the gate of the PMOS transistor and the length of each of the fingers of the NMOS transistor is greater than the length of each of the fingers of the PMOS transistor.

Abstract: In a semiconductor device for protecting an electrostatic discharge and a method of fabricating the same, a gate electrode is disposed on a semiconductor substrate of first conductivity type, and a heavily doped region and a vertical lightly doped region surround the heavily doped region. The heavily doped region and vertical lightly doped region have a second conductivity type and are disposed in the semiconductor substrate on both sides of the gate electrode. The vertical lightly doped region has a lower impurity concentration and a larger depth than the heavily doped regions. A horizontal lightly doped region, which has a lower impurity concentration than the vertical lightly doped region, is further disposed in an upper side of the vertical lightly doped region.

Abstract: In a semiconductor device for protecting an electrostatic discharge and a method of fabricating the same, a gate electrode is disposed on a semiconductor substrate of first conductivity type, and a heavily doped region and a vertical lightly doped region surround the heavily doped region. The heavily doped region and vertical lightly doped region have a second conductivity type and are disposed in the semiconductor substrate on both sides of the gate electrode. The vertical lightly doped region has a lower impurity concentration and a larger depth than the heavily doped regions. A horizontal lightly doped region, which has a lower impurity concentration than the vertical lightly doped region, is further disposed in an upper side of the vertical lightly doped region.

Abstract: An electrostatic discharge protection circuit, which is arranged between a pad input terminal and a circuit device, includes a first diode protection circuit unit and a second diode protection circuit unit. The first diode protection circuit unit includes a first diode and a second diode, which are connected in parallel between the pad input terminal and an input voltage terminal and face opposite directions. The second diode protection circuit unit includes a third diode and a fourth diode, which are connected in parallel between the pad input terminal and a substrate terminal and face opposite directions. The electrostatic discharge protection circuit can make electrostatic discharge current flow by making all the diodes operate only in a forward direction, irrespective of electrostatic discharge stress generated from the outside.