Patents by Inventor Won John Choi
Won John Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9418936Abstract: A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.Type: GrantFiled: March 15, 2016Date of Patent: August 16, 2016Assignee: SK hynix Inc.Inventors: Jae Hwan Kim, Won John Choi
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Publication number: 20160197040Abstract: A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.Type: ApplicationFiled: March 15, 2016Publication date: July 7, 2016Inventors: Jae Hwan KIM, Won John CHOI
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Patent number: 9318435Abstract: A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.Type: GrantFiled: April 2, 2014Date of Patent: April 19, 2016Assignee: SK HYNIX INC.Inventors: Jae Hwan Kim, Won John Choi
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Publication number: 20160035669Abstract: A semiconductor device may include a global line coupled to a source, and a plurality of local lines coupled to a plurality of targets, respectively, and coupled to the global line. The local lines may be configured to have cross-sectional areas. The cross-sectional areas may increase in proportion to distances from the source to the respective targets.Type: ApplicationFiled: July 28, 2015Publication date: February 4, 2016Inventor: Won John Choi
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Publication number: 20150214153Abstract: A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.Type: ApplicationFiled: April 2, 2014Publication date: July 30, 2015Applicant: SK HYNIX INC.Inventors: Jae Hwan KIM, Won John CHOI
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Patent number: 8283787Abstract: A semiconductor device includes a through-silicon-via arranged to couple a plurality of stacked semiconductor chips, an interconnection line coupled to the through-silicon-via at one side and arranged to couple the through-silicon-via to the semiconductor chip, an internal interconnection line disposed at the other side of the interconnection line and intersected with the interconnection line, and at least one first contact disposed to couple the internal interconnection line to the interconnection line. A region of the interconnection line in which the internal interconnection line is disposed is equally divided, and an area between the divided regions is removed.Type: GrantFiled: July 9, 2010Date of Patent: October 9, 2012Assignee: Hynix Semiconductor Inc.Inventors: Won-John Choi, Su-Hyun Kim
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Publication number: 20120007187Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.Type: ApplicationFiled: September 23, 2011Publication date: January 12, 2012Inventors: Nam Gyu RYU, Ho Ryong KIM, Won John CHOI, Jae Hwan KIM, Seoung Hyun KANG, Young Hee YOON
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Publication number: 20110291290Abstract: A semiconductor device includes a through-silicon-via arranged to couple a plurality of stacked semiconductor chips, an interconnection line coupled to the through-silicon-via at one side and arranged to couple the through-silicon-via to the semiconductor chip, an internal interconnection line disposed at the other side of the interconnection line and intersected with the interconnection line, and at least one first contact disposed to couple the internal interconnection line to the interconnection line. A region of the interconnection line in which the internal interconnection line is disposed is equally divided, and an area between the divided regions is removed.Type: ApplicationFiled: July 9, 2010Publication date: December 1, 2011Inventors: Won-John Choi, Su-Hyun Kim
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Patent number: 8053346Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.Type: GrantFiled: April 25, 2008Date of Patent: November 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Nam Gyu Ryu, Ho Ryong Kim, Won John Choi, Jae Hwan Kim, Seoung Hyun Kang, Young Hee Yoon
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Publication number: 20110156169Abstract: A semiconductor apparatus comprises a semiconductor substrate; a group of PMOS transistors formed on a predetermined portion of the semiconductor substrate; a group of NMOS transistors disposed adjacent to the group of PMOS transistors on the semiconductor substrate; a guard ring region formed between the group of PMOS transistors and the group of NMOS transistors; and a current detouring unit formed in the guard ring region and configured to discharge current produced by plasma ions towards the semiconductor substrate.Type: ApplicationFiled: July 26, 2010Publication date: June 30, 2011Applicant: Hynix Semiconductor Inc.Inventors: Won John CHOI, Nam Gyu Ryu
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Publication number: 20080265335Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.Type: ApplicationFiled: April 25, 2008Publication date: October 30, 2008Inventors: Nam Gyu RYU, Ho Ryong KIM, Won John CHOI, Jae Hwan KIM, Seoung Hyun KANG, Young Hee YOON