Abstract: There are many validity tests, such as a depth test, used to determine which pixels are valid or invalid in a 3D computer graphic rendering process. It is not necessary to display the invalid pixels on the screen, because these pixels are hidden behind other objects or other windows. The invalid pixels will eventually be discarded in the rendering process later. Conventional designs pushed pixels into a frame buffer, no matter these pixels pass the validity tests or not. The present invention presents a pipelined bubble squeezer to separate pixels into a valid group and a invalid group. The pixels in the invalid group are not pushed into the frame buffer for achieving a better performance. The pipelined bubble squeezer behaves like many bubbles floating up to the top eventually through an interconnection network of cells.

Abstract: A three-dimensional graphics display system has a computational unit for computing the attribute values of several successive pixels at the same time for a specific graphics attribute. By time-sharing the computational unit, multiple graphics attributes can be computed using only one computational unit. The attribute values for each graphics attribute of the successive pixels are buffered in a special merge FIFO which may have a group of output data paths for sending out the attribute values of a group of pixels each computation cycle. There are multiple merge FIFOs for buffering the attribute values of the multiple graphics attributes. After the attribute values for all the desired graphics attributes for a group of pixels are available, the buffered attribute values for the group of pixels are sent out through their respective data paths. By using a pipeline architecture in the design, a high performance and low cost computation engine is provided for the three-dimensional graphics display system.

Abstract: An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f2<f1<f2 or 0.5f1<f2<f1, where f2 is the write frequency if f1 is the read frequency, or vice versa. A FIFO in accordance with the present invention comprises a dual port random access memory, a read pointer, a write pointer, a synchronization circuit and a status indicator. In the FIFO design, the read pointer indicating the read address is a simple sequential counter, and the write pointer indicating the write address is a Gray code counter. Gray code to sequential count converters are used to convert the Gray codes to sequential counts. The synchronization circuit synchronizes the write pointer and the read pointer using a read clock. A status indicator with simple circuits is provided to indicate if the FIFO is almost full or empty.

Abstract: An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one destination processor associated therewith for servicing the interrupt request. An interrupt controller in accordance with the present invention applies latched interrupt requests to a priority compare tree which serves to prioritize received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. Similar determinations are made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt.

Abstract: A modified three-pixel antialiasing method wherein the closest pixel from a displayed line has a constant display intensity includes the steps of locating a first pixel having a shortest distance along an axis of the pixel matrix array from the line, determining the shortest distance, calculating pixel intensity for the first pixel by multiplying a maximum intensity of the first pixel with a constant value, locating a second pixel having a second shortest distance along the axis from the line, locating a third pixel having a third shortest distance along the axis from the line, calculating pixel intensity for the second pixel, and calculating pixel intensity for the third pixel.