Abstract: The present invention relates to a renal denervation catheter which detects contact of a heating electrode with a renal vessel surface and detects reaction sensitivity of a target nerve by a detection electrode so as to excise only the target nerve. To this end, the renal denervation catheter is disclosed, wherein the renal denervation catheter comprises: a catheter housing; an electrode part provided in a housing, emitting a contact detection RF signal for contact with the inner wall of the renal vessel according to a contact detection mode, and emitting a denervation RF signal for renal denervation according to a denervation mode; a control part for allowing to enter the denervation mode when a contact detection feedback signal value generated by the contact detection mode satisfies a defined condition.

Abstract: Disclosed is an operating method of a memory system that includes a plurality of memory blocks, the operating method including a first step of copying, in order to recover sudden power-off of the memory system, data of an open block to a selected block among the plurality of memory blocks while maintaining map data associated with the open block and open block identification information; a second step of erasing the open block; and a third step of copying the data, which is copied to the selected block, to the erased open block.

Abstract: A memory system includes a memory device including memory blocks, and a controller configured to in response to a program request or a read request for a selected memory block among the memory blocks being received from a host, store first data to which a first logical address is allocated in a cache group, generate a first entry for the first data stored in the cache group, and in response to second data to which the first logical address is allocated being stored in the cache group after the first data is stored in the cache group, generate a second entry for the second data.

Abstract: The present technology relates to an electronic device. The storage device according to the present technology may include a memory device and a memory controller. The memory device may include a plurality of memory blocks. The memory controller may control the memory device to perform a recovery operation for a first sudden power off on a target block on which a program operation is stopped due to the first sudden power off among the plurality of memory blocks, and perform a program operation of storing lock data including information indicating completion of the recovery operation for the first sudden power off in a page next to a page on which the recovery operation is completed in the target block.

Abstract: A memory system includes at least one semiconductor memory device including a plurality of memory blocks in which an original data stripe including a plurality of unit data and parity data is stored, and a controller configured to control an operation of the semiconductor memory device. The controller performs an error correction operation on one or more unit data received from the semiconductor memory device, and generates data for recovery based on remaining data except for first and second unit data among the plurality of unit data, in response to a first error correction failure for the first unit data among the plurality of unit data and a second error correction failure for the second unit data.

Abstract: Disclosed is an operating method of a memory system that includes a plurality of memory blocks, the operating method including a first step of copying, in order to recover sudden power-off of the memory system, data of an open block to a selected block among the plurality of memory blocks while maintaining map data associated with the open block and open block identification information; a second step of erasing the open block; and a third step of copying the data, which is copied to the selected block, to the erased open block.

Abstract: A memory system includes a memory device including memory blocks, and a controller configured to in response to a program request or a read request for a selected memory block among the memory blocks being received from a host, store first data to which a first logical address is allocated in a cache group, generate a first entry for the first data stored in the cache group, and in response to second data to which the first logical address is allocated being stored in the cache group after the first data is stored in the cache group, generate a second entry for the second data.

Abstract: A memory system includes at least one semiconductor memory device including a plurality of memory blocks in which an original data stripe including a plurality of unit data and parity data is stored, and a controller configured to control an operation of the semiconductor memory device. The controller performs an error correction operation on one or more unit data received from the semiconductor memory device, and generates data for recovery based on remaining data except for first and second unit data among the plurality of unit data, in response to a first error correction failure for the first unit data among the plurality of unit data and a second error correction failure for the second unit data.

Abstract: The present technology relates to an electronic device. The storage device according to the present technology may include a memory device and a memory controller. The memory device may include a plurality of memory blocks. The memory controller may control the memory device to perform a recovery operation for a first sudden power off on a target block on which a program operation is stopped due to the first sudden power off among the plurality of memory blocks, and perform a program operation of storing lock data including information indicating completion of the recovery operation for the first sudden power off in a page next to a page on which the recovery operation is completed in the target block.

Abstract: A system and a method for generating a digital storyboard in which characters with various emotions are produced. The digital storyboard generating system includes an emotion-expressing character producing unit to produce an emotion-based emotion-expressing character, and a storyboard generating unit to generate storyboard data using the emotion-expressing character. Optionally, cartoon-rendering is performed on the storyboard data to generate an image, where the image is output to the user.

Abstract: A system and a method for generating a digital storyboard in which characters with various emotions are produced. The digital storyboard generating system includes an emotion-expressing character producing unit to produce an emotion-based emotion-expressing character, and a storyboard generating unit to generate storyboard data using the emotion-expressing character. Optionally, cartoon-rendering is performed on the storyboard data to generate an image, where the image is output to the user.

Abstract: A packet data processing apparatus of a wide-band wireless local loop (W-WLL) system includes a local area network (LAN) controller for performing an interface with a LAN and transmitting and receiving a packet data. The system further includes an high-level data link control (HDLC) controller for transmitting and receiving a packet data to and from a subscriber wireless connection unit through an HDLC channel, a dynamic random access memory having a first buffer for storing a mobile image packet data transmitted between the HDLC controller and the LAN controller and a second buffer for storing a packet data other than the mobile image, and a CPU for performing the corresponding control function of a packet data routing unit. Buffers are utilized and managed separately for transmitting mobile image data and general data from the packet data routing unit of the W-WLL system to the Internet.

Abstract: A packet data processing apparatus of a wide-band wireless local loop (W-WLL) system includes a local area network (LAN) controller for performing an interface with a LAN and transmitting and receiving a packet data. The system further includes an high-level data link control (HDLC) controller for transmitting and receiving a packet data to and from a subscriber wireless connection unit through an HDLC channel, a dynamic random access memory having a first buffer for storing a mobile image packet data transmitted between the HDLC controller and the LAN controller and a second buffer for storing a packet data other than the mobile image, and a CPU for performing the corresponding control function of a packet data routing unit. Buffers are utilized and managed separately for transmitting mobile image data and general data from the packet data routing unit of the W-WLL system to the Internet.