Patents by Inventor Wonil Kwon

Wonil Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9406579
    Abstract: A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 2, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DaeSik Choi, JoungIn Yang, Sang Mi Park, WonIl Kwon, YiSu Park
  • Patent number: 9401289
    Abstract: A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active area of the semiconductor wafer from the first surface partially through the semiconductor wafer. A protective coating is formed over the first surface and into the trench. A lamination tape is applied over the protective coating. A portion of a second surface of the semiconductor wafer is removed by backgrinding or wafer thinning to expose the protecting coating in the trench. A die attach film is applied over the second surface of the semiconductor wafer. A cut or modified region is formed in the die attach film under the trench using a laser. The semiconductor wafer is expanded to separate the cut or modified region of the die attach film and singulate the semiconductor wafer.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: July 26, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: MinJung Kim, KyungHoon Lee, JoungIn Yang, WonIl Kwon, DaeSik Choi
  • Publication number: 20140070410
    Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.
    Type: Application
    Filed: November 20, 2013
    Publication date: March 13, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, JoonYoung Choi, WonIl Kwon
  • Publication number: 20130320519
    Abstract: A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active area of the semiconductor wafer from the first surface partially through the semiconductor wafer. A protective coating is formed over the first surface and into the trench. A lamination tape is applied over the protective coating. A portion of a second surface of the semiconductor wafer is removed by backgrinding or wafer thinning to expose the protecting coating in the trench. A die attach film is applied over the second surface of the semiconductor wafer. A cut or modified region is formed in the die attach film under the trench using a laser. The semiconductor wafer is expanded to separate the cut or modified region of the die attach film and singulate the semiconductor wafer.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 5, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: MinJung Kim, KyungHoon Lee, JoungIn Yang, WonIl Kwon, DaeSik Choi
  • Publication number: 20130300004
    Abstract: A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: DaeSik Choi, JoungIn Yang, Sang Mi Park, WonIl Kwon, YiSu Park
  • Publication number: 20130154107
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: MinJung Kim, DaeSik Choi, WonIl Kwon
  • Patent number: 8304296
    Abstract: A method of manufacture of a semiconductor packaging system includes: providing a substrate; mounting a semiconductor chip to the substrate; mounting a pillar ball having a ball height electrically connected to the substrate; mounting an interposer above the semiconductor chip and electrically connected to the pillar ball; and wherein: mounting the interposer or mounting the substrate includes connecting the pillar ball to a pillar base having a base height substantially less than the ball height of the pillar ball and the pillar base having vertical sides not covered by the pillar ball.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: November 6, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: ChanHoon Ko, Junwoo Myung, Wonil Kwon
  • Publication number: 20120211900
    Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.
    Type: Application
    Filed: February 21, 2011
    Publication date: August 23, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: DaeSik Choi, JoonYoung Choi, WonIl Kwon
  • Publication number: 20110316155
    Abstract: A method of manufacture of a semiconductor packaging system includes: providing a substrate; mounting a semiconductor chip to the substrate; mounting a pillar ball having a ball height electrically connected to the substrate; mounting an interposer above the semiconductor chip and electrically connected to the pillar ball; and wherein: mounting the interposer or mounting the substrate includes connecting the pillar ball to a pillar base having a base height substantially less than the ball height of the pillar ball and the pillar base having vertical sides not covered by the pillar ball.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Inventors: ChanHoon Ko, Junwoo Myung, Wonil Kwon