Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

Abstract: A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

Abstract: A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

Abstract: A semiconductor memory module may include a random access memory, a nonvolatile memory, a buffer memory, and a controller configured to execute a reading operation on the buffer memory in response to an activation of a control signal. The controller may be further configured to execute a flush operation of storing first data, which are stored in the random access memory, in the nonvolatile memory, according to a result of the reading operation.

Abstract: Apparatus and method for decoding a Space-Time Block Coded (STBC) signal. The decoding apparatus includes a channel estimator for estimating a real equivalent channel based on a coded signal; a channel converter for decomposing the real equivalent channel to a unit matrix and a subchannel; a receive signal converter for converting the coded signal to a real equivalent receive signal and converting the real equivalent receive signal to a converted receive signal based on the unit matrix; and a detector for detecting an estimate of a transmit signal by performing a maximum likelihood decoding using the converted receive signal and the subchannel. Since the transmit signal candidates are independent of each other, the complexity of the maximum likelihood decoding can be decreased. With the lowered complexity of the receiver, the power consumption for the decoding can be reduced and the high-speed data can be transmitted more easily in the actual mobile communication environment.

Abstract: Apparatus and method for decoding a Space-Time Block Coded (STBC) signal. The decoding apparatus includes a channel estimator for estimating a real equivalent channel based on a coded signal; a channel converter for decomposing the real equivalent channel to a unit matrix and a subchannel; a receive signal converter for converting the coded signal to a real equivalent receive signal and converting the real equivalent receive signal to a converted receive signal based on the unit matrix; and a detector for detecting an estimate of a transmit signal by performing a maximum likelihood decoding using the converted receive signal and the subchannel. Since the transmit signal candidates are independent of each other, the complexity of the maximum likelihood decoding can be decreased. With the lowered complexity of the receiver, the power consumption for the decoding can be reduced and the high-speed data can be transmitted more easily in the actual mobile communication environment.