Abstract: Discussed is a liquid crystal display device. The liquid crystal display device of the present disclosure comprises a liquid crystal panel, a backlight unit disposed under the liquid crystal panel and including a light guide plate and an optical sheet over the light guide plate, and a bottom frame including a horizontal surface and a side surface, wherein first and second fastening protrusions are provided at an outer surface of the side surface of the bottom frame.

Abstract: Discussed is a liquid crystal display device. The liquid crystal display device of the present disclosure comprises a liquid crystal panel, a backlight unit disposed under the liquid crystal panel and including a light guide plate and an optical sheet over the light guide plate, and a bottom frame including a horizontal surface and a side surface, wherein first and second fastening protrusions are provided at an outer surface of the side surface of the bottom frame.

Abstract: The present application discloses an array substrate comprising an active layer; and a plurality of touch electrodes in a same layer as the active layer.

Abstract: Embodiments of an access point (AP), station (STA) and method for communication in accordance with frame formats of varying sizes of pilot portions are generally described herein. The AP may transmit, to the STA, a first downlink frame in accordance with a first downlink frame format. The AP may receive, from the STA, a phase noise measurement of the STA. The AP may select, based at least partly on the received phase noise measurement, a downlink frame format to enable a phase noise compensation at the STA. The AP may generate a downlink frame in accordance with the second downlink frame format, and may transmit the second downlink frame to the STA. In some cases, the first and second downlink frame formats may be based on different ratios of pilot portions to data portions.

Abstract: A thin film transistor and a fabrication method thereof, and a display device are provided. The thin film transistor comprises an active layer, wherein, a target oxide is formed at a portion of the active layer where an oxygen content is higher than oxygen contents of other portions of the active layer, and a carrier mobility of the target oxide is greater than that of other portions of the active layer.

Abstract: The present application discloses an array substrate comprising an active layer; and a plurality of touch electrodes in a same layer as the active layer.

Abstract: A thin film transistor and a fabrication method thereof, and a display device are provided. The thin film transistor comprises an active layer, wherein, a target oxide is formed at a portion of the active layer where an oxygen content is higher than oxygen contents of other portions of the active layer, and a carrier mobility of the target oxide is greater than that of other portions of the active layer.

Abstract: A memory integrated circuit which is driven with a low power and reduced the cell area and a method for manufacturing the same. A plurality of active regions having an H-shape with four source regions and common drain region are formed on a semiconductor substrate. Four word lines each having a different source correspondingly pass through each of the four source regions of an active region, thereby forming four transistors driven, independently. These four transistors are designed so as to share one bit line, thereby reducing the driving voltage of the transistor to 1/4 Vcc. With a low power driving source, four transistors and a capacitor are formed on a small area to thereby reduce the cell size to 33% and even more.

Abstract: An electrostatic discharge (ESD) protecting transistor and a method for fabricating the same, capable of consuming a high voltage or overcurrent applied to a semiconductor circuit device and thereby protecting the circuit device from the high voltage or overcurrent. The ESD protecting transistor is of an asymmetric charge coupled MOS transistor structure having a highly doped buried layer capable of dispersing a current flux, thereby removing an instant ESD impact and reducing generation of heat caused by a concentration of high current flux. Accordingly, an effect of improving the resistance characteristic to the ESD impact is provided.

Abstract: The present invention relates to a method for forming a TiNO metallic barrier layer acting as a diffusion barrier to intercept the diffusing of the Si atoms between metal layers, the method comprising the steps of: forming a TiN film through a sputtering equipment using Ar and N.sub.2 gas; implanting N.sub.2 O gas on the upper part of the TiN film; and annealing the resulting structure at N.sub.2 atmosphere for diffusing oxygen ions, thereby forming said resulting structure into uniform TiNO film.

Abstract: A memory integrated circuit which is driven with a low power and reduced cell area and a method for manufacturing the same. A plurality of active regions having an H-shape with four source regions and a common drain region are formed on a semiconductor substrate. Four word lines, each having a different source correspondingly pass through each of the four source regions of an active region, thereby forming four transistors driven, independently. These four transistors are designed so as to share one bit line thereby reducing the driving voltage of the transistor to 1/4 Vcc. With a low power driving source, four transistors and a capacitor are formed on a small area to thereby reduce the cell size to 33% and even more.

Abstract: The present invention discloses a high voltage cut-off semiconductor device that can prevent unstable supply voltage of several volts that is not cut off by a conventional electrostatic discharge protection circuit from being applied to an internal circuit and apply only stable supply voltage to the internal circuit, thereby enhancing the characteristics of the semiconductor device and shortening the channel length of the transistors forming the internal circuit by suing a constant voltage circuit having a zener diode.