Abstract: Disclosed are a solid electrolyte and method of manufacturing the same. The solid electrolyte may include a core including a first electrolyte represented by Chemical Formula 1, and a shell including a second electrolyte represented by Chemical Formula 2, and disposed on a surface of the core. LiaPSbX1c??[Chemical Formula 1] Here, a satisfies an equation 4?a?7, b satisfies an equation 3?b?7, c satisfies an equation 0?c?2, and X1 includes Br or I. LidPSeX2f??[Chemical Formula 2] Here, d satisfies an equation 4?d?7, e satisfies an equation 3?e?7, f satisfies an equation 0?f?2, X2 includes Cl or Br, and an ionic radius of X1 is greater than an ionic radius of X2.

Abstract: The present invention relates to an operation mode setting circuit and a method for setting thereof. The circuit includes a mode register, an internal control signal generator, a mode control signal generator, a first output unit, a second output unit, a first decoder and a second decoder. The mode register provides internal address signals by inputting external address signals. The internal control signal generator generates an internal control signal in response to an external control signal. The mode control signal generator generates a test mode control signal or mode register set control signal by combining the internal address signals in response to a mode register set write signal and the internal control signal. The first output unit outputs a corresponding address signal among the internal address signals as a first internal address signal in response to the mode register set control signal.

Abstract: In a semiconductor memory integrated circuit device, power consumption and clock noise are reduced by providing a plurality of separately controlled internal clock signal generators. All of the internal clock signal generators receive an external clock signal, so as to provide respective internal clock signals that are synchronized with the external clock signal. However, each of the internal clock signal generators is separately controlled depending upon the present operating mode of the memory, so that individual internal clock signals are generated only when required.