Abstract: A fuel cell apparatus of the disclosure includes a case having defined therein a first accommodation space and a second accommodation space, which are isolated from each other by a partition wall, a first cover covering the first accommodation space in the case, a second cover covering the second accommodation space in the case, a power distribution unit disposed in the first accommodation space, and a power conversion unit disposed in the second accommodation space.

Abstract: The present disclosure relates to a memory system capable of encrypting and storing data, and a memory controller. The memory controller may include a first interface configured to perform data Communication with a first external device, a second interface configured to generate a signal for controlling an operation of a second extern& device and transmit the signal; and a processor configured to receive, from the first external device, a data write command to write data to the second external device, encrypt the data by using one of a plurality of keys stored in a key area provided in the first external device in response to the data write command, and then control the encrypted data to be written to the second external device.

Abstract: A fuel cell vehicle includes a cell stack, a DC level converter, an output unit, a first switching unit disposed between a positive output terminal of the DC level converter and a positive input terminal of the output unit, a second switching unit disposed between a negative output terminal of the DC level converter and a negative input terminal of the output unit, a resistor and a third switching unit connected to each other in series between the positive output terminal of the DC level converter and the negative output terminal of the DC level converter, a fourth switching unit disposed between a contact point between the resistor and the third switching unit and the positive input terminal of the output unit, and a controller for controlling switching operation of the first, second, third and fourth switching units according to an operation mode.

Abstract: A method of operating a storage device for reducing write latency. The storage device determines whether to support write data support (WDS), fetches a write command selectively including an instant write flag when WDS is supported, updates an address mapping table regarding a controller memory buffer (CMB) without an host direct memory access (HDMA) operation in response to the fetched write command, and generates write command completion message corresponding to the write command.

Abstract: A data processing method of a memory controller includes receiving first partial data of a last sector data among a plurality of sector data to be stored in an n-th page of a non-volatile memory in a program operation; padding the first partial data with first dummy data and generating a first error correction code (ECC) parity in the program operation; and transferring the first partial data and the first ECC parity to the non-volatile memory in the program operation, while refraining from transferring the first dummy data to the non-volatile memory. Related devices and systems are also described.

Abstract: A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.

Abstract: A data processing method of a memory controller includes receiving first partial data of a last sector data among a plurality of sector data to be stored in an n-th page of a non-volatile memory in a program operation; padding the first partial data with first dummy data and generating a first error correction code (ECC) parity in the program operation; and transferring the first partial data and the first ECC parity to the non-volatile memory in the program operation, while refraining from transferring the first dummy data to the non-volatile memory. Related devices and systems are also described.

Abstract: A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.