Abstract: System and method for the management of bit plane resources are presented. Because of the scarcity of processing element (PE) memory in a SIMD architecture, it is important to ensure that it is used with optimal efficiency. The Invention discloses methods for managing PE memory at runtime such that nearly 100% utilization is achieved. The method employed allows memory to be allocated and deallocated in single bit plane increments. Runtime allocation and deallocation occurs continuously such that it is impossible to guarantee availability of contiguous blocks of PE memory. The method employed by the invention allows scattered bit planes to be used without the necessity of expending execution time to perform “garbage collection”.

Abstract: System and method for the execution of instructions from an auxiliary data stream in a parallel processing system are presented. The data processing system includes a program sequencer, an array processor and data input/output logic. Rather than increasing the program memory size to accommodate the most extreme application requirements, a method for executing from an auxiliary data stream via an “expansion interface” is provided. Specifically, program instructions are stored within and provided from the system's frame buffer. An additional data stream including program sequencer instructions is added to the memory controller capabilities. During execution from the expansion interface, the sequencing logic of the program sequencer receives and executes instructions from this auxiliary data stream in lieu of execution from the program memory.

Abstract: System and method for reading and writing pixel aligned subframes from a frame buffer in a parallel processing system are disclosed. Optimal bandwidth access of the frame buffer requires that data be moved in bursts having multiple data words. Subframes are specified at X and Y locations within the image frame with a resolution of one pixel. In addition, subframes within a row may overlap each other and consecutive subframe rows may also overlap. Memory control logic of the invention provides pixel packing and unpacking and storing selected pixel data in a cache memory. Reading and writing to the frame buffer is provided in a manner that makes optimal use of the frame buffer internal architecture. Other capabilities of the memory control logic include decimation of pixel data during input, suppression of redundant frame buffer writes, and accessing image frame data in an interlaced manner.

Abstract: In an image processing system, computations on pixel data may be performed by an array of bit-serial processing elements (PEs). A bit-serial PE is implemented with minimal logic in order to provide the highest possible density of PEs constituting the array. Improvements to the PE architecture are achieved to enable operations to execute in fewer clock cycles. However, care is taken to minimize the additional logic required for improvements. The bit-serial nature of the PE is also maintained in order to promote the highest possible density of PEs in an array. PE improvements described herein include enhancements to improve performance for sum of absolute difference (SAD) operations, division, multiplication, and transform (e.g. FFT) shuffle steps.

Abstract: In an image processing system, high density storage of bit-plane data is provided in a secondary or page memory as well as high bandwidth access to the data by an image processor. The page memory provides storage of data not currently being processed. The page memory may also be part of a system that provides input and output of image data to and from the image processor. The image data may be handled outside the image processor in a packed pixel form and be converted between that form and bit-line form which the page memory stores during input and output. The bit-line data may be gathered into bit-planes for use by the image processor during movement of data from the page memory to the processing logic.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array.

Abstract: An apparatus for processing data has a plurality of single-bit processing elements coupled together to form an m×n processing element array, where m is an integer number of rows and n is an integer number of columns. Each processing element has addressable storage for storing pixel data in an array format in which each addressable storage holds all of the bits associated with one pixel; and the processing element array includes a mechanism for providing direct read/write access to the addressable storage located in any addressed row of the processing element array without requiring that data be passed through other rows of the array.

Abstract: Bit-serial processors quickly multiply multiple-bit operands using significantly fewer clock cycles as compared to conventional bit-serial implementations. Exemplary embodiments process groups of operand bits simultaneously to provide the significant speed increases. Advantageously, however, the exemplary embodiments utilize logic and memory architectures which are fully compatible with, and fully useful for, conventional bit-serial applications, and the embodiments thus provide fast multiple-bit multiplications while at the same time providing all of the advantages typically associated with conventional bit-serial processors.

Abstract: Methods and apparatus for quickly dividing multiple-bit operands using bit-serial processors include strategies for eliminating the number of steps required to execute conventional division operations. According to an exemplary embodiment, a conditional subtraction step, based on a quotient bit computed during a given pass, is combined with a compare step which is used to compute a next quotient bit and which, according to conventional techniques, is ordinarily computed during a subsequent pass. Additionally, exemplary embodiments provide a zero/non-zero mask for denominator bits which extend beyond a current most significant remainder bit during a given pass. As a result, not all denominator bits need be considered during every pass. Advantageously, the methods and apparatus of the invention can provide approximately a 3 to 1 speed improvement as compared to conventional techniques.

Abstract: A format for representing floating point numbers reduces the overhead typically associated with parsing floating point numbers and thereby provides for significantly improved processing speeds, particularly for bit-serial processors. According to an exemplary single-precision embodiment, numbers are represented using a 36-bit data format. Extra bits in the representation according to the invention allow certain conditions, such as overflow/underflow and the zero-ness of a number, to be detected and asserted quickly. Other conditions, such as denormalization are subsumed into normal processing through the extension of an exponent range in the representation.