Patents by Inventor Woo-Hyun Park
Woo-Hyun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11997801Abstract: A printed circuit board includes: a core portion including a cavity in one surface thereof; first and second penetration holes disposed in a bottom surface of the cavity and penetrating through the core portion; an electronic component disposed in the cavity; and an insulating material filling the cavity and each of the first and second penetration holes, wherein a sidewall of the cavity is higher than the electronic component.Type: GrantFiled: May 10, 2022Date of Patent: May 28, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Woo Seok Yang, Jae Han Park, Jung Hyun Cho
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Publication number: 20240153075Abstract: The electronic device for recommending an AI-based melanoma biopsy site according to an exemplary embodiment of the present invention includes a processor which classifies a skin image that is input by using a classification model as melanoma or nevus, identifies melanoma features in the skin image by using a generation model when the skin image is classified as melanoma to generate an image from which the melanoma features are removed, and compares the skin image with the generated image to identify at least one candidate biopsy site.Type: ApplicationFiled: November 1, 2023Publication date: May 9, 2024Inventors: Ju Hee HAN, Ji Ho PARK, Young-Min PARK, Ji-Hyun LEE, Chul Hwan BANG, Woo Hyup LEE, Jeong Wook MOON
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Publication number: 20240149819Abstract: The present disclosure relates to an interior material for a vehicle and a method for molding the interior material for the vehicle, and more specifically the method for molding an interior material for a vehicle according to the present disclosure includes heating a skin inserted into an upper end heater and a lower end heater spaced apart from each other; preforming the heated skin using an upper mold having a mold temperature set to have a set shape and a lower mold having a second mold temperature; and pressing the preformed skin and a core using a 1-1 mold and a 1-2 mold having set mold temperatures.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Applicants: HYUNDAI MOTOR COMPANY, Kia Corporation, KBI Dongkook Ind. Co., Ltd.Inventors: Jae Hyun An, In Soo Han, Woo Hyun Lim, Kyu Ha Yoo, Dong II Son, Dong Hyuk Choi, Chang Woo Kang, Chang Bok Park, Wan Gyu Choi
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Publication number: 20240146953Abstract: There is provided a method of decoding an image, the method comprising: decoding information for motion information prediction of a current block from a bitstream, predicting motion information of the current block based on the information, refining motion information of the current block by using the decoded information and the predicted motion information of the current block and reconstructing the current block based on the refined motion information of the current block.Type: ApplicationFiled: December 22, 2023Publication date: May 2, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Gun BANG, Hui Yong KIM, Gwang Hoon PARK, Woo Woen GWUN, Tae Hyun KIM, Won Jun LEE
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Patent number: 11973209Abstract: A positive electrode active material for a secondary battery includes a lithium composite transition metal oxide including nickel (Ni), cobalt (Co), and manganese (Mn), wherein the lithium composite transition metal oxide has a layered crystal structure of space group R3m, includes the nickel (Ni) in an amount of 60 mol % or less based on a total amount of transition metals, includes the cobalt (Co) in an amount greater than an amount of the manganese (Mn), and is composed of single particles.Type: GrantFiled: June 7, 2019Date of Patent: April 30, 2024Assignee: LG Chem, Ltd.Inventors: Eun Hee Lee, Seong Bae Kim, Young Su Park, Yi Rang Lim, Hong Kyu Park, Song Yi Yang, Byung Hyun Hwang, Woo Hyun Kim
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Patent number: 11963403Abstract: A display device includes a first substrate. A transistor is disposed on the first substrate. A light-emitting element is connected to the transistor. An insulating layer is disposed between the transistor and the light-emitting element. A second substrate at least partially overlaps the first substrate. A color conversion layer is disposed on the second substrate. The insulating layer includes a first insulating layer and a second insulating layer. A distance between the first insulating layer and the first substrate is less than a distance between the second insulating layer and the first substrate. The first insulating layer includes a light blocking material.Type: GrantFiled: August 13, 2019Date of Patent: April 16, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Seung Hyun Park, Joo Sun Yoon, Woo Sik Jun, Yun-Mo Chung
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Patent number: 11205604Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.Type: GrantFiled: October 1, 2018Date of Patent: December 21, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Choon Kim, Woo Hyun Park, Eon Soo Jang, Young Sang Cho
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Patent number: 11004760Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.Type: GrantFiled: January 24, 2020Date of Patent: May 11, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Hyun Park, Jae Choon Kim
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Patent number: 10964618Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.Type: GrantFiled: August 1, 2019Date of Patent: March 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-woo Lee, Kyung-suk Oh, Yung-cheol Kong, Woo-hyun Park, Jong-bo Shim, Jae-myeong Cha
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Patent number: 10707196Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the seType: GrantFiled: October 17, 2018Date of Patent: July 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Choon Kim, Young-Deuk Kim, Woo-Hyun Park
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Publication number: 20200168522Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.Type: ApplicationFiled: August 1, 2019Publication date: May 28, 2020Inventors: Jang-woo Lee, Kyung-suk Oh, Yung-cheol Kong, Woo-hyun Park, Jong-bo Shim, Jae-myeong Cha
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Publication number: 20200161201Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.Type: ApplicationFiled: January 24, 2020Publication date: May 21, 2020Inventors: Woo Hyun Park, Jae Choon KIM
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Patent number: 10553513Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.Type: GrantFiled: March 15, 2018Date of Patent: February 4, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Hyun Park, Jae Choon Kim
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Publication number: 20190237382Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.Type: ApplicationFiled: October 1, 2018Publication date: August 1, 2019Inventors: Jae Choon KIM, Woo Hyun PARK, Eon Soo JANG, Young Sang CHO
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Publication number: 20190198489Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the seType: ApplicationFiled: October 17, 2018Publication date: June 27, 2019Inventors: Jae-Choon KIM, Young-Deuk KIM, Woo-Hyun PARK
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Publication number: 20190057918Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.Type: ApplicationFiled: March 15, 2018Publication date: February 21, 2019Inventors: Woo Hyun PARK, Jae Choon KIM
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Publication number: 20190017999Abstract: The present invention relates to a micro-fluid chip for blood vessel formation. The micro-fluid chip of the present invention is constituted by first to fifth channels arranged adjacent to one another on a substrate in sequence, and two or more micro-structures or micro-posts having a gap therebetween are disposed on the interface that each channel forms together with an adjacent channel while contacting the same. Each channel performs a fluidic interaction with a different channel through the gap formed by the micro-structures, and biochemical materials can move therethrough. The micro-fluid chip, according to the present invention, provides a micro-blood vessel having a flat and continuous blood vessel interface outside a body. Furthermore, cancer angiogenesis, cancer intravasation, and cancer extravasation can be modeled using the micro-fluid chip of the present invention. In addition, the micro-fluid chip of the present invention can be used to screen candidate anti-cancer drugs.Type: ApplicationFiled: September 4, 2015Publication date: January 17, 2019Inventors: Noo Li Jeon, Min Hwan Chung, Su Jung Oh, Woo Hyun Park, Hyun Jae Lee, Hyun Yul Ryu, Su Dong Kim
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Publication number: 20120005622Abstract: An apparatus to display a three-dimensional (3D) User Interface (UI) includes a display panel to display a 3D UI comprising main menu polygonal cells; a sensing unit to sense a user selection of a target main menu polygonal cell; and a control unit to execute a function of the selected target main menu polygonal cell.Type: ApplicationFiled: May 24, 2011Publication date: January 5, 2012Applicant: PANTECH CO., LTD.Inventors: Woo Hyun PARK, Su Jin KIM
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Publication number: 20090309641Abstract: An edge triggered flip-flop including at least one inverter and at least one transmission gate section. Each transmission gate section includes an upper part having a first transmission gate and a second transmission gate connected in series, the first transmission gate being controlled in accordance with a clock signal, and the second transmission gate being controlled in accordance with an enable clock signal. Each transmission gate section also includes a lower part having a third transmission gate and a fourth transmission gate connected in series, the third transmission gate being controlled complementarily to the first transmission gate in accordance with the clock signal, and the fourth transmission gate being controlled complementarily to the second transmission gate in accordance with the enable clock signal.Type: ApplicationFiled: June 10, 2009Publication date: December 17, 2009Inventor: Woo-Hyun Park
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Publication number: 20090150845Abstract: Embodiments relate to a cell library for an application specific integrated circuit (ASIC). Embodiments relate to a method for defining current drive capacity of a cell library, which may define an amount of various kinds of drive current in a single pin and driving current in the cell library. According to embodiments, a method may include defining a current drive capacity for the cell library, receiving a timing arc selected by an external control switch, checking a current drive level defined in the input timing arc, searching for an index table defined in the checked current drive level, and driving a current written on the searched index table.Type: ApplicationFiled: December 3, 2008Publication date: June 11, 2009Inventor: Woo-Hyun Park