Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

Abstract: A hair dryer including a main body; a fan inside the main body to generate a flow of air; and a nozzle connected to the main body so that the air flows into the nozzle. The nozzle includes a nozzle body having an inner space, a nozzle partition wall inside the nozzle body dividing the inner space into first and second nozzle passages, a plurality of first nozzle holes formed in the nozzle body to communicate with the first nozzle passage, and a plurality of second nozzle holes formed in the nozzle body to communicate with the second nozzle passage. The nozzle is configured so that air flowing into the first nozzle passage is discharged through the first nozzle holes in a first direction, and air flowing into the second nozzle passage is discharged through the second nozzle holes in a second direction that is different from the first direction.

Abstract: An electronic device is disclosed, including: a housing including a nonconductive area, a first printed circuit board (PCB) including a cavity and a fill-cut area, overlapping the nonconductive area, a first antenna module including at least one antenna array disposed in the cavity of the first PCB, a support frame coupled to one surface of the first PCB, supporting the first antenna module, a grip sensing pad surrounding the cavity and overlapping the fill-cut area, and a sensing circuit unit electrically connected to the grip sensing pad, configured to control an output power of the first antenna module based on inputs received via the grip sensing pad.

Abstract: An electronic device includes a housing including a speaker hole, and a speaker module in the housing. The speaker module includes a speaker including a first surface outputting an audio signal, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface. The speaker module includes a first housing including a first portion including a first opening overlapping the first surface when viewed from above and a second portion disposed on the first portion, a second housing attached to the first housing and including a duct extending from the first opening to the speaker hole, a first space extending from the first opening through the duct to the speaker hole, and a second space in the first housing, being disconnected from the first space by the speaker. The second portion is configured to seal the second space.

Abstract: A negative electrode for a lithium metal battery, a lithium metal battery including the same, and a method of preparing the negative electrode are provided. The negative electrode includes a negative electrode current collector, and a protective layer disposed on the negative electrode current collector. The protective layer includes a first protective layer and a second protective layer disposed between the first protective layer and the negative electrode current collector. The first protective layer includes porous nanostructure particles, and the second protective layer includes polar inorganic particles.

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip on the package substrate, a sealing layer on the package substrate and at least partially covering the first semiconductor chip and including an upper surface, a first side surface, and a first inclined surface extending between the upper surface and the first side surface, and a first marking pattern in or on the first inclined surface of the sealing layer.

Abstract: Disclosed is a semiconductor device including a substrate, conductive structures on the substrate and extending in parallel to each other in a first direction, and a first interlayer dielectric layer in first and second trenches between the conductive structures. A width in a second direction of the first trench may be less than a width in the second direction of the second trench. The first interlayer dielectric layer may include a lower interlayer dielectric layer and an upper interlayer dielectric layer on the lower interlayer dielectric layer, sequentially stacked. A mechanical strength of the upper interlayer dielectric layer may be greater than a mechanical strength of the lower interlayer dielectric layer.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: A substrate processing apparatus includes a chamber having an internal space configured to process a substrate loaded therein; a light source configured to emit light on the substrate to harden a photoresist pattern coated on the substrate; and a transparent division part provided between the substrate and the light source, wherein the transparent division part divides the chamber into a first space, in which the light source is provided, and a second space, in which the substrate is provided.

Abstract: A semiconductor device may include a substrate including a chip region and an edge region enclosing the chip region, and at least one coarse key pattern divided into fine key patterns on the edge region, extend in a first direction and are spaced apart from each other in a second direction crossing the first direction. Each of the fine key patterns may include a first key pattern, extending in the first direction, and a second key pattern including a first portion extending along a side surface of the first key pattern, and a second portion extending along an opposite side surface of the first key pattern. A width of each of the first and second portions may be smaller than a width of the first key pattern, when measured in the second direction.

Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

Abstract: A method of manufacturing a display apparatus, the method includes removing an oxide layer formed on a surface of a substrate by utilizing a hydrofluoric acid gas and an ammonia gas, and thermally treating the substrate from which the oxide layer has been removed. A flow ratio between the hydrofluoric acid gas and the ammonia gas is about 0.8:1 to about 1:1.

Abstract: A semiconductor device has a substrate and two semiconductor die disposed over the substrate. A thermal interface material is disposed over the semiconductor die. A conductive epoxy is disposed on a ground pad of the substrate. A lid is disposed over the semiconductor die. The lid includes a sidewall over the ground pad between the semiconductor die. The lid physically contacts the conductive epoxy and thermal interface material.

Abstract: A two-dimensional perovskite material, a dielectric material including the same, and a multi-layered capacitor. The two-dimensional perovskite material includes a layered metal oxide including a first layer having a positive charge and a second layer having a negative charge which are laminated, a monolayer nanosheet exfoliated from the layered metal oxide, a nanosheet laminate of a plurality of the monolayer nanosheets, or a combination thereof, wherein the two-dimensional perovskite material a first phase having a two-dimensional crystal structure is included in an amount of greater than or equal to about 80 volume %, based on 100 volume % of the two-dimensional perovskite material, and the two-dimensional perovskite material is represented by Chemical Formula 1.

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

Abstract: A method of manufacturing a display apparatus includes forming a semiconductor layer on a substrate, forming an insulating layer on the semiconductor layer, forming a photoresist pattern on the insulating layer, forming, by etching the insulating layer, a contact hole exposing at least a portion of the semiconductor layer, and performing a primary cleaning of the insulating layer in which the contact hole is formed using a cleaning gas including a fluorine-containing gas and a hydrogencontaining gas.

Abstract: A battery protection circuit includes: a charging control switch connected in series to a big current path between a battery module configured with a plurality of cells connected in series and a plurality of pack terminals; a battery controller for controlling the charging control switch based on cell voltages of the cells; and a plurality of first protection circuits connected to the respective cells on the big current path, and intercepting or allowing a current flowing to the corresponding cell based on the cell voltage of the corresponding cell from among the cells, wherein the first protection circuits respectively include at least one switch connected in series between neighboring cells or between one of the cells and a first pack terminal from among the pack terminals, and a cell controller for controlling the at least one switch according to a cell voltage of the corresponding cell.

Abstract: A color conversion panel includes a substrate, a low refractive layer disposed on one surface of the substrate and including a carbosilane-siloxane copolymer, a color conversion layer disposed on the low refractive layer and including a color conversion member and a planarization layer covering the low refractive layer and the color conversion layer, wherein the low refractive layer has a refractive index of less than or equal to 1.30 in a wavelength of 500 nm to 550 nm, and the color conversion member includes a quantum dot, and a manufacturing method thereof is provided.

Abstract: A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.