Patents by Inventor Wook Hyun Kwon
Wook Hyun Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136430Abstract: A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.Type: ApplicationFiled: May 24, 2023Publication date: April 25, 2024Inventors: Jongmin SHIN, Wook Hyun KWON, Su-Hyeon KIM, Jun Mo PARK, Kyu Bong CHOI
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Publication number: 20220406939Abstract: The present disclosure provides a semiconductor device with improved element performance and reliability. The semiconductor device includes a lower insulating layer, a fin-shaped insulating layer that is on the lower insulating layer and extends in a first direction, a field insulating layer that is on the lower insulating layer and extends in the first direction, a plurality of gate structures that are on the fin-shaped insulating layer and include a gate electrode intersecting the fin-shaped insulating layer, a source/drain region that is on the fin-shaped insulating layer and is between the gate structures, and an active pattern that is on the fin-shaped insulating layer and penetrates the gate electrode and is electrically connected to the source/drain region, where the gate electrode extends in a second direction intersecting the first direction.Type: ApplicationFiled: February 9, 2022Publication date: December 22, 2022Inventors: Jong Pil Kim, Wook Hyun Kwon
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Patent number: 9564340Abstract: A method of manufacturing a semiconductor device includes forming a plurality of active fins over a semiconductor substrate, sequentially forming first and second hard mask layers over the active fins, forming a first hard mask pattern by etching the second hard mask layer, trimming the first hard mask pattern to form a trimmed hard mask pattern, forming a first photo resist pattern over the first hard mask layer, forming second hard mask patterns by etching the first hard mask layer by using the trimmed hard mask pattern and the first photo resist pattern as an etching mask, and forming active fin patterns by etching the active fins by using the second hard mask patterns as an etching mask.Type: GrantFiled: December 2, 2015Date of Patent: February 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gi-bong Lee, Wook-hyun Kwon, Kyung-soo Kim, Seon-ah Nam, Yeon-ho Park, Nak-jin Son
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Publication number: 20160225635Abstract: A method of manufacturing a semiconductor device includes forming a plurality of active fins over a semiconductor substrate, sequentially forming first and second hard mask layers over the active fins, forming a first hard mask pattern by etching the second hard mask layer, trimming the first hard mask pattern to form a trimmed hard mask pattern, forming a first photo resist pattern over the first hard mask layer, forming second hard mask patterns by etching the first hard mask layer by using the trimmed hard mask pattern and the first photo resist pattern as an etching mask, and forming active fin patterns by etching the active fins by using the second hard mask patterns as an etching mask.Type: ApplicationFiled: December 2, 2015Publication date: August 4, 2016Inventors: Gi-bong LEE, Wook-hyun KWON, Kyung-soo KIM, Seon-ah NAM, Yeon-ho PARK, Nak-jin SON
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Patent number: 8354708Abstract: Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.Type: GrantFiled: April 15, 2011Date of Patent: January 15, 2013Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Wook-Hyun Kwon, Byung-Gook Park, Yun-Heub Song, Yoon Kim
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Publication number: 20110302363Abstract: A non-volatile memory device can include a buried bit line in a substrate of a non-volatile memory device and a self-aligned shallow trench isolation region in the substrate that is self-aligned to the buried bit line.Type: ApplicationFiled: August 22, 2011Publication date: December 8, 2011Inventor: Wook Hyun KWON
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Patent number: 8022462Abstract: Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines.Type: GrantFiled: April 25, 2008Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Wook Hyun Kwon
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Publication number: 20110194356Abstract: Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.Type: ApplicationFiled: April 15, 2011Publication date: August 11, 2011Applicants: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY INDUSTRY FOUNDATIONInventors: Wook-Hyun KWON, Byung-Gook PARK, Yun-Heub SONG, Yoon KIM
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Patent number: 7928501Abstract: Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.Type: GrantFiled: July 6, 2009Date of Patent: April 19, 2011Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Wook-Hyun Kwon, Byung-Gook Park, Yun-Heub Song, Yoon Kim
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Publication number: 20100001339Abstract: Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars.Type: ApplicationFiled: July 6, 2009Publication date: January 7, 2010Inventors: Wook-Hyun Kwon, Byung-Gook Park, Yun-Heub Song, Yoon Kim
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Patent number: 7586135Abstract: Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.Type: GrantFiled: November 30, 2006Date of Patent: September 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Wook-Hyun Kwon, Ki-Nam Kim, Chan-Kwang Park, Soon-Moon Jung, Sang-Pil Sim
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Patent number: 7547943Abstract: A NAND-type non-volatile memory device includes a substrate and a device isolation layer disposed on the substrate to define an active region. First and second selection transistors are disposed in the active region, such that each of the first and second selection transistors has a recessed channel. A plurality of memory transistors is disposed in the active region between the first selection transistor and the second selection transistor.Type: GrantFiled: December 22, 2004Date of Patent: June 16, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-Kwan Cho, Eun-Suk Cho, Wook-Hyun Kwon
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Patent number: 7468924Abstract: A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read from the programmed selected memory cells. It is determined whether each of the programmed memory cells has been successfully programmed based on the results of the reading step. The programming of memory cells that have been determined to have been successfully programmed are inhibited. The programming, reading, determining and inhibiting steps are repeated until each of the selected memory cells has been determined to have been successfully programmed. A memory cell that has been previously determined to have been successfully programmed and inhibited is uninhibited and subsequently re-programmed when it is determined that the previously inhibited memory cell is no longer successfully programmed.Type: GrantFiled: December 9, 2006Date of Patent: December 23, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Wook-Hyun Kwon
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Publication number: 20080265303Abstract: Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines.Type: ApplicationFiled: April 25, 2008Publication date: October 30, 2008Inventor: Wook Hyun Kwon
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Publication number: 20080094923Abstract: A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read from the programmed selected memory cells. It is determined whether each of the programmed memory cells has been successfully programmed based on the results of the reading step. The programming of memory cells that have been determined to have been successfully programmed are inhibited. The programming, reading, determining and inhibiting steps are repeated until each of the selected memory cells has been determined to have been successfully programmed. A memory cell that has been previously determined to have been successfully programmed and inhibited is uninhibited and subsequently re-programmed when it is determined that the previously inhibited memory cell is no longer successfully programmed.Type: ApplicationFiled: December 9, 2006Publication date: April 24, 2008Inventor: Wook-Hyun Kwon
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Patent number: 7338860Abstract: Embodiments of the present invention are directed to methods for forming non-volatile memory devices. A substrate is provided that has a cell region, a first peripheral region, and second peripheral region. A tunnel insulating layer and a preliminary blocking insulating layer are formed on the substrate in the cell region. A blocking insulating layer and a conductive layer are formed on the substrate in the cell region, the first peripheral region, and the second peripheral region. The conductive layer and the blocking insulating layer in the first and second peripheral regions are removed to expose at least a portion of the substrate in the first and second peripheral regions, while leaving the conductive layer and the blocking insulating layer in the cell region.Type: GrantFiled: November 7, 2005Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Wook-Hyun Kwon
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Publication number: 20070268749Abstract: A method of operating a non-volatile memory device is disclosed. The memory cell includes a channel region separating a source region and a drain region, a tunnel insulating layer, a charge storage layer, and a gate electrode formed over the channel region. The method includes applying a negative voltage to the gate electrode and applying a positive voltage to at least one of the source and drain regions to inject holes into the tunnel insulating layer and thereby remove electrons trapped in the tunnel insulating layer.Type: ApplicationFiled: May 22, 2007Publication date: November 22, 2007Inventors: Dae-Mann Kim, Wook-Hyun Kwon, Ki-Nam Kim, Chan-Kwang Park, Sang-Pil Sim
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Patent number: 7276415Abstract: A method of forming a contactless nonvolatile memory device includes preparing a semiconductor substrate including a cell array region, forming a plurality of mask patterns being parallel to each other on the semiconductor substrate in the cell array region, etching the semiconductor substrate using the mask patterns as an etch mask to form a plurality of recess regions, forming a gate insulating layer on sidewalls and bottoms of the recess regions, forming a floating gate layer on an upper surface of the semiconductor substrate to fill the recess regions, planarizing the floating gate layer to expose upper surfaces of the mask patterns and to form floating gate patterns in the recess regions, forming buried impurity diffusion regions in the semiconductor substrate under the mask patterns, forming an intergate dielectric layer, forming a control gate layer, and patterning the control gate layer, the intergate dielectric layer and the floating gate pattern to form a plurality of parallel word lines crossing thType: GrantFiled: October 31, 2006Date of Patent: October 2, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Wook-Hyun Kwon, Chan-Kwang Park, Sang-Pil Sim
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Publication number: 20070176214Abstract: Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.Type: ApplicationFiled: November 30, 2006Publication date: August 2, 2007Inventors: Wook-Hyun Kwon, Ki-Nam Kim, Chan-Kwang Park, Soon-Moon Jung, Sang-Pil Sim
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Patent number: 7230853Abstract: Selective erase method for a flash memory device including a group of memory cells arranged in rows and columns include performing an erase operation on the group of memory cells and verifying the erase operation on the group of memory cells to determine threshold voltages of the memory cells. At least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage is identified. A further erase operation is performed on the group of memory cells excluding memory cells of the at least one row of memory cells including memory cells having a threshold voltage lower than a desired erase threshold voltage.Type: GrantFiled: October 7, 2004Date of Patent: June 12, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Wook-Hyun Kwon, Jung-In Han