Abstract: According to one aspect of the disclosure, there is provided a mount bracket for installation of communication device in a structure, the mount bracket including: a bracket body coupled to the structure; a bracket base, to which the communication device is fixed, coupled to the bracket body and rotates to cover the bracket body; and a connection member provided at one end of the bracket body to rotatably connect the bracket base to the bracket body, wherein the bracket base includes an anti-detachment structure for preventing separation from the bracket body during rotation.

Abstract: A system on chip includes a display serial interface (DSI) host device, a camera serial interface (CSI) host device, a first register, and a loopback control circuit. The first register is configured to store a first flag indicating whether the system on chip is operating in a loopback mode or a non-loopback mode. The loopback control circuit is configured to loop back data generated by the DSI host device to the CSI host device in response to the first flag indicating that the system on chip is operating in the loopback mode.

Abstract: A header processing device includes an error detector, a controller, and a reallocator. The error detector detects an error in a header in a packet and outputs a header error detection result. The controller selects first and second information from the header based on information corresponding to a type of the header and the header error detection result. The reallocator merges the first and second information and generates a header with a common format different from a format of the header.

Abstract: A packet transmitter includes a higher layer transmission block and a lower layer transmission block. The higher layer transmission block generates a higher layer data signal including payload data and a header for each packet of a plurality of packets based on an application layer data signal and an application layer control signal. The higher layer transmission block outputs the header after the payload data through the higher layer data signal. The lower layer transmission block generates a lower layer data signal including the header and the payload data for each packet based on the higher layer data signal and a higher layer control signal. The lower layer transmission block outputs the payload data after the header through the lower layer data signal.

Abstract: A header processing device includes an error detector, a controller, and a reallocator. The error detector detects an error in a header in a packet and outputs a header error detection result. The controller selects first and second information from the header based on information corresponding to a type of the header and the header error detection result. The reallocator merges the first and second information and generates a header with a common format different from a format of the header.

Abstract: A system on chip includes a display serial interface (DSI) host device, a camera serial interface (CSI) host device, a first register, and a loopback control circuit. The first register is configured to store a first flag indicating whether the system on chip is operating in a loopback mode or a non-loopback mode. The loopback control circuit is configured to loop back data generated by the DSI host device to the CSI host device in response to the first flag indicating that the system on chip is operating in the loopback mode.

Abstract: A packet transmitter includes a higher layer transmission block and a lower layer transmission block. The higher layer transmission block generates a higher layer data signal including payload data and a header for each packet of a plurality of packets based on an application layer data signal and an application layer control signal. The higher layer transmission block outputs the header after the payload data through the higher layer data signal. The lower layer transmission block generates a lower layer data signal including the header and the payload data for each packet based on the higher layer data signal and a higher layer control signal. The lower layer transmission block outputs the payload data after the header through the lower layer data signal.