Abstract: A display apparatus includes a base substrate, an active pattern on the base substrate including a source region, a drain region, and a channel region that is doped between the source region and the drain region, the channel region including polycrystalline silicon, and a gate electrode overlapping the channel region of the active pattern. The channel region may include a lower portion, an upper portion, and an intermediate portion between the upper portion and the lower portion, and a dopant density of the lower portion may be 80% or more of a dopant density of the upper portion.

Abstract: A display device includes a substrate, a buffer layer on the substrate, a first semiconductor layer of a first transistor on the buffer layer, a first insulating layer disposed on the first semiconductor layer, a first gate electrode of the first transistor on the first insulating layer, a second insulating layer on the first gate electrode, and a second semiconductor layer of a second transistor disposed on the second insulating layer. A difference between a first distance between a lower side of the buffer layer and an upper side of the second insulating layer and a second distance between an upper side of the first semiconductor layer and an upper side of the second insulating layer is 420 to 520 angstroms.

Abstract: A pixel including a light emitting element, a first transistor connected between a first node and the light emitting element to control current flowing from a first power supply to a second power supply, a second transistor connected between a data line and the first transistor to be turned on by an ith first scan signal, a third transistor including a P-type TFT connected between the first transistor and the first node to be turned on by the ith first scan signal and, a fourth transistor including an N-type TFT connected between the first node and an initialization power supply line to be turned on by an i?1th scan signal, and a first connection line connected between the third and fourth transistors to electrically connect semiconductor patterns thereof, in which the first connection line is disposed on the third and fourth transistors and contacts the semiconductor patterns thereof.

Abstract: A scan driver includes stage circuits, each including: a first circuit including a control terminal (CT) connected to a first node (N1), and connecting/disconnecting a previous scan line of a previous stage circuit to a second node (N2) based on a control signal (CS); a second circuit including a CT connected to a clock signal line, and connecting one of a first power voltage line (FPVL) and a second power voltage line (SPVL) to the N1 based on a CS; a third circuit including a CT connected to the N2, and connecting one of the N1 and the SPVL to a third node (N3) based on a CS; a fourth circuit including a CT connected to the N3, and connecting one of the FPVL and the SPVL to a current scan line based on a CS; and a first capacitor connecting the CT of the third circuit and the SPVL.

Abstract: A transistor substrate may include a base substrate, and a switching transistor and a driving transistor provided on the base substrate. The driving transistor includes: an active pattern provided on the base substrate and including a source region, a drain region spaced apart from the source region, and a channel region provided between the source region and the drain region; a gate electrode at least partially overlapping the active pattern; a gate insulating film provided between the active pattern and the gate electrode; a source electrode insulated from the gate electrode and connected to the source region; a drain electrode insulated from the gate electrode and connected to the drain region; and at least one dummy hole adjacent to the channel region.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a substrate; a plurality of transistors formed on the substrate; and a light-emitting device connected to the plurality of transistors, wherein the transistor includes a gate electrode, the plurality of transistors include a first transistor and a second transistor of which lateral wall slope angles of the gate electrode are different from each other, and the first transistor further includes a doping control member formed on a lateral wall of the gate electrode.

Abstract: A display device includes a substrate, a buffer layer on the substrate, a first semiconductor layer of a first transistor on the buffer layer, a first insulating layer disposed on the first semiconductor layer, a first gate electrode of the first transistor on the first insulating layer, a second insulating layer on the first gate electrode, and a second semiconductor layer of a second transistor disposed on the second insulating layer. A difference between a first distance between a lower side of the buffer layer and an upper side of the second insulating layer and a second distance between an upper side of the first semiconductor layer and an upper side of the second insulating layer is 420 to 520 angstroms.

Abstract: An organic light emitting diode display having a lightly doped region formed in a transistor for simplifying manufacturing process and reducing manufacturing costs is provided. The organic light emitting diode display includes: a substrate, a transistor on the substrate, and an organic light emitting diode (OLED) connected to the transistor, wherein the transistor includes a semiconductor member on the substrate, an insulating member on the semiconductor member, a source member and a drain member disposed on the semiconductor member and respectively disposed at opposite sides of the insulating member, and a gate electrode on the insulating member, wherein each of the source member and the drain member includes a plurality of layers having different impurity doping concentrations.

Abstract: A display device includes: a flexible substrate; a semiconductor layer on the flexible substrate; a passivation layer on the semiconductor layer; an alignment member layer on the passivation, the alignment member layer including a first alignment member and a second alignment member in a same layer; a first insulation layer on the alignment member layer and the passivation layer; a gate electrode on the first insulation layer; a second insulation layer on the first insulation layer and the gate electrode; and a source electrode and a drain electrode on the second insulation layer and spaced apart from each other, wherein the first alignment member and the second alignment member are spaced apart from each other with the gate electrode therebetween.

Abstract: A blind display device includes a plurality of curved display panels, a support, and a plurality of rotators. Each of the curved display panels includes a curved display area between a flat display area and a bezel area. The support guides movement of the curved display panels. The rotators couple corresponding ones of the curved display panels to the support and rotate corresponding ones of the curved display panels.

Abstract: A manufacturing method of a thin film transistor array panel according to an exemplary embodiment of the present invention includes forming an amorphous silicon thin film on a substrate. A lower region of the amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film by irradiating a laser beam with an energy density of from about 150 mj/cm2 to about 250 mj/cm2 to the amorphous silicon thin film.

Abstract: An organic light emitting diode display having a lightly doped region formed in a transistor for simplifying manufacturing process and reducing manufacturing costs is provided. The organic light emitting diode display includes: a substrate, a transistor on the substrate, and an organic light emitting diode (OLED) connected to the transistor, wherein the transistor includes a semiconductor member on the substrate, an insulating member on the semiconductor member, a source member and a drain member disposed on the semiconductor member and respectively disposed at opposite sides of the insulating member, and a gate electrode on the insulating member, wherein each of the source member and the drain member includes a plurality of layers having different impurity doping concentrations.

Abstract: A manufacturing method of a thin film transistor array panel according to an exemplary embodiment of the present invention includes forming an amorphous silicon thin film on a substrate. A lower region of the amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film by irradiating a laser beam with an energy density of from about 150 mj/cm2 to about 250 mj/cm2 to the amorphous silicon thin film.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a substrate; a plurality of transistors formed on the substrate; and a light-emitting device connected to the plurality of transistors, wherein the transistor includes a gate electrode, the plurality of transistors include a first transistor and a second transistor of which lateral wall slope angles of the gate electrode are different from each other, and the first transistor further includes a doping control member formed on a lateral wall of the gate electrode.

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, an oxide semiconductor layer, an oxide buffer layer, a protective layer, and source and drain electrodes. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate. The oxide semiconductor layer is formed on the gate insulating layer and includes a source, a channel and a drain region. The oxide buffer layer is formed on the oxide semiconductor layer, and has a carrier concentration lower than that of the oxide semiconductor layer. The protective layer is formed on the oxide buffer layer and the gate insulating layer, and has contact holes formed therein so that the oxide buffer layer in the source and drain regions are exposed therethrough. The source and drain electrodes are coupled with the oxide buffer layer in the source and drain regions through the contact holes.

Abstract: A blind display device includes a plurality of curved display panels, a support, and a plurality of rotators. Each of the curved display panels includes a curved display area between a flat display area and a bezel area. The support guides movement of the curved display panels. The rotators couple corresponding ones of the curved display panels to the support and rotate corresponding ones of the curved display panels.

Abstract: Exemplary embodiments provide compositions for a solution process, electronic devices fabricated using the same, and fabrication methods thereof. An oxide nano-structure is formed using a sol-gel process. An oxide thin film transistor is formed using the oxide nano-structure.

Abstract: Exemplary embodiments provide compositions for a solution process, electronic devices fabricated using the same, and fabrication methods thereof. An oxide nano-structure is formed using a sol-gel process. An oxide thin film transistor is formed using the oxide nano-structure.

Abstract: Exemplary embodiments provide compositions for a solution process, electronic devices fabricated using the same, and fabrication methods thereof. An oxide nano-structure is formed using a sol-gel process. An oxide thin film transistor is formed using the oxide nano-structure.

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, an oxide semiconductor layer, an oxide buffer layer, a protective layer, and source and drain electrodes. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate. The oxide semiconductor layer is formed on the gate insulating layer and includes a source, a channel and a drain region. The oxide buffer layer is formed on the oxide semiconductor layer, and has a carrier concentration lower than that of the oxide semiconductor layer. The protective layer is formed on the oxide buffer layer and the gate insulating layer, and has contact holes formed therein so that the oxide buffer layer in the source and drain regions are exposed therethrough. The source and drain electrodes are coupled with the oxide buffer layer in the source and drain regions through the contact holes.