Abstract: A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region. The drift layer and semiconductor may be doped with a first type of impurity and the well may be doped with a second type of impurity. Through this arrangement, an improved distribution of carriers may be formed in the drift layer.

Abstract: Example embodiments relate to semiconductor devices and/or methods of manufacturing the same. According to example embodiments, a semiconductor device may include a first heterojunction field effect transistor (HFET) on a first surface of a substrate, and a second HFET. A second surface of the substrate may be on the second HFET. The second HFET may have different properties (characteristics) than the first HFET. One of the first and second HFETs may be of an n type, while the other thereof may be of a p type. The first and second HFETs may be high-electron-mobility transistors (HEMTs). One of the first and second HFETs may have normally-on properties, while the other thereof may have normally-off properties.

Abstract: A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region. The drift layer and semiconductor may be doped with a first type of impurity and the well may be doped with a second type of impurity. Through this arrangement, an improved distribution of carriers may be formed in the drift layer.

Abstract: Example embodiments relate to semiconductor devices and/or methods of manufacturing the same. According to example embodiments, a semiconductor device may include a first heterojunction field effect transistor (HFET) on a first surface of a substrate, and a second HFET. A second surface of the substrate may be on the second HFET. The second HFET may have different properties (characteristics) than the first HFET. One of the first and second HFETs may be of an n type, while the other thereof may be of a p type. The first and second HFETs may be high-electron-mobility transistors (HEMTs). One of the first and second HFETs may have normally-on properties, while the other thereof may have normally-off properties.

Abstract: A method of measuring a shifted extent of a shifted epitaxy layer by an N+ buried layer using difference between contact resistances is described. An N-type buried layer comprising a stepped portion is formed at a P-type substrate. An epitaxy layer is formed, comprising a stepped portion, on the N-type buried layer. A plug is formed in the epitaxy layer. An insulating layer is formed on the epitaxy layer. A plurality of contacts are formed in the insulating layer. Resistances of the plurality of contacts are measured and a shifting extent of the stepped portion of the epitaxy layer is calculated using the plurality of contact resistances.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate including first and second well areas doped with second conductive ions, a third well area in the first well and doped with the second conductive ions, a base area in the third well and doped with first conductive ions, an emitter area in the third well and doped with the second conductive ions, an emitter electrode on the emitter area, a first contact plug in contact with the emitter electrode, a second contact plug in contact with the base area, a collector area in the second well and doped with the second conductive ions, and a third contact plug in contact with the collector area.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: A method for manufacturing a semiconductor device includes steps of injecting a hole current into an N drift region while a constant voltage is applied to a P+ anode of a lateral insulated gate bipolar transistor, such that a majority of the hole current passes through a P+ cathode of the lateral insulated gate bipolar transistor via a P+ buried layer. Therefore, a hole-current path located under an N+ cathode area of a LIGBT structure is eliminated, thus securing sufficient latch-up current density.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: Disclosed is a method of measuring a pattern shift in a semiconductor device. The method measures a mobility or shift distance of a stepped portion occurring between a buried layer surface and a substrate surface during an epitaxial process on the buried layer. The method includes the steps of: recognizing a first width ratio of a metallic wiring over a stepped pattern in an insulation film shifted by a certain distance and measuring a first capacitance value of a capacitor including the metallic wiring, forming a first pattern having a second width ratio different from the first width ratio, measuring a capacitance value of the first pattern, forming multiple patterns having width ratios different from the first and second width ratios, measuring capacitance values of the multiple patterns, establishing reference values using the measured capacitance values, and comparing the first capacitance value with any one of the established reference values to recognize a shift distance of the stepped pattern.

Abstract: A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the third well region to form a base electrode pattern; forming a spacer on a sidewalls of the base electrode pattern; implanting first conductivity type ions in the semiconductor substrate to form an emitter region adjacent to the base electrode pattern and form a collector region in the second well region; and performing a diffusion process to form a base region adjacent to the emitter region.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: Provided is a method of fabricating a lateral double diffused MOSFET. In the method, ions are implanted onto a substrate to form a body region of the LDMOS transistor using a photoresist pattern as an ion implantation mask. Herein, the photoresist can be patterned to have a slope of with an angle in the range of 87° to 88°.

Abstract: A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the semiconductor substrate; forming an emitter electrode pattern on the third well region, and forming a collector electrode pattern on the second well region; forming spacers at sidewalls of the emitter and collector electrode patterns; performing a diffusion process to form an emitter region of a first conductivity on the third well region and to form a collector region of a first conductivity on the second well region; implanting ions of a second conductivity in the third well region to form a base region; and removing the emitter electrode and collector region patterns.

Abstract: A method for forming a LOCOS layer in a semiconductor device includes steps of oxidizing a high voltage region of the semiconductor device to form a LOCOS layer in the high voltage region; and etching the LOCOS layer according to a pattern.

Abstract: A method of measuring a shifted extent of a shifted epitaxy layer by an N+ buried layer using difference between contact resistances is described. An N-type buried layer comprising a stepped portion is formed at a P-type substrate. An epitaxy layer is formed, comprising a stepped portion, on the N-type buried layer. A plug is formed in the epitaxy layer. An insulating layer is formed on the epitaxy layer. A plurality of contacts are formed in the insulating layer. Resistances of the plurality of contacts are measured and a shifting extent of the stepped portion of the epitaxy layer is calculated using the plurality of contact resistances.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate including first and second well areas doped with second conductive ions, a third well area in the first well and doped with the second conductive ions, a base area in the third well and doped with first conductive ions, an emitter area in the third well and doped with the second conductive ions, an emitter electrode on the emitter area, a first contact plug in contact with the emitter electrode, a second contact plug in contact with the base area, a collector area in the second well and doped with the second conductive ions, and a third contact plug in contact with the collector area.

Abstract: Disclosed is a method of measuring a pattern shift in a semiconductor device. The method measures a mobility or shift distance of a stepped portion occurring between a buried layer surface and a substrate surface during an epitaxial process on the buried layer. The method includes the steps of: recognizing a first width ratio of a metallic wiring over a stepped pattern in an insulation film shifted by a certain distance and measuring a first capacitance value of a capacitor including the metallic wiring, forming a first pattern having a second width ratio different from the first width ratio, measuring a capacitance value of the first pattern, forming multiple patterns having width ratios different from the first and second width ratios, measuring capacitance values of the multiple patterns, establishing reference values using the measured capacitance values, and comparing the first capacitance value with any one of the established reference values to recognize a shift distance of the stepped pattern.

Abstract: Methods for fabricating LDMOS transistors are disclosed. A disclosed method includes: forming a device isolation structure in a semiconductor substrate through an STI process; forming a photoresist pattern exposing the device isolation structure; forming double diffused wells by implanting ions into the substrate; removing the exposed device isolation structure; and removing the photoresist pattern.