Patents by Inventor Woong-Sun Lee
Woong-Sun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120177Abstract: A substrate processing method is provided. The substrate processing method comprises loading a substrate onto a substrate support inside a chamber, forming a plasma inside the chamber, providing a first DC pulse signal to an electromagnet that generates a magnetic field inside the chamber and processing the substrate with the plasma, wherein the first DC pulse signal is repeated at a first period including a first section and a second section subsequent to the first section, the first DC pulse signal has a first level during the first section, and the first DC pulse signal has a second level different from the first level during the second section.Type: ApplicationFiled: September 19, 2023Publication date: April 11, 2024Inventors: Ji Mo LEE, Dong Hyeon NA, Myeong Soo SHIN, Woong Jin CHEON, Kyung-Sun KIM, Jae Bin KIM, Tae-Hwa KIM, Seung Bo SHIM
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Patent number: 8796834Abstract: A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines.Type: GrantFiled: May 31, 2011Date of Patent: August 5, 2014Assignee: SK Hynix Inc.Inventors: Jin Ho Bae, Qwan Ho Chung, Woong Sun Lee
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Publication number: 20140014958Abstract: A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines.Type: ApplicationFiled: January 9, 2013Publication date: January 16, 2014Applicant: SK HYNIX INC.Inventors: Tac Keun OH, Jae Sung OH, Kwon Whan HAN, Woong Sun LEE, Seon Kwang JEON
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Patent number: 8618637Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.Type: GrantFiled: August 15, 2008Date of Patent: December 31, 2013Assignee: Hynix Semiconductor Inc.Inventors: Han Jun Bae, Woong Sun Lee
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Patent number: 8558380Abstract: A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer.Type: GrantFiled: February 3, 2012Date of Patent: October 15, 2013Assignee: SK Hynix Inc.Inventors: Si Han Kim, Woong Sun Lee
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Publication number: 20130236993Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: ApplicationFiled: April 24, 2013Publication date: September 12, 2013Applicant: SK HYNIX INC.Inventors: Woong Sun LEE, Qwan Ho CHUNG
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Patent number: 8445322Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: GrantFiled: September 23, 2011Date of Patent: May 21, 2013Assignee: SK Hynix Inc.Inventors: Woong Sun Lee, Qwan Ho Chung
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Patent number: 8441116Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.Type: GrantFiled: May 7, 2012Date of Patent: May 14, 2013Assignee: Hynix Semiconductor Inc.Inventors: Woong Sun Lee, Qwan Ho Chung, Il Hwan Cho, Sang Joon Lim, Jong Woo Yoo, Jin Ho Bae, Seung Hyun Lee
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Patent number: 8399998Abstract: A semiconductor package includes a semiconductor chip having a first surface, a second surface located opposite the first surface, and side surfaces connecting the first and second surfaces. The semiconductor chip includes bonding pads disposed on the first surface and having a molding member formed to cover the first surface of the semiconductor chip. The molding member is formed so as to expose the side surfaces of the semiconductor chip. The semiconductor chip also includes bonding members having first ends electrically connected to the respective bonding pads and second ends that are connected to and opposite the first ends. The second ends are exposed from side surfaces of the molding member after passing through the molding member so as to allow various electrical connections.Type: GrantFiled: October 23, 2009Date of Patent: March 19, 2013Assignee: Hynix Semiconductor Inc.Inventors: Ki Young Kim, Sung Ho Hyun, Myung Geun Park, Woong Sun Lee
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Publication number: 20120217637Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.Type: ApplicationFiled: May 7, 2012Publication date: August 30, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Woong Sun LEE, Qwan Ho CHUNG, Il Hwan CHO, Sang Joon LIM, Jong Woo YOO, Jin Ho BAE, Seung Hyun LEE
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Publication number: 20120205798Abstract: A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer.Type: ApplicationFiled: February 3, 2012Publication date: August 16, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Si Han KIM, Woong Sun LEE
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Patent number: 8129627Abstract: A circuit board includes a semiconductor chip having an upper surface and side surfaces connected to the upper surface. A bonding pad is disposed on the upper surface of the semiconductor chip. A bump is disposed on the bonding pad and projects from the bonding pad by a predetermined height. A circuit board body has a recess part, and the semiconductor chip is positioned in the recess part so that the circuit board body covers the upper surface and the side surfaces of the semiconductor chip while exposing an end of the bump. A wiring line is disposed on the circuit board body and part of the wiring line is positioned over the bump. An opening is formed in a portion of the part of the wiring line over the bump to expose the bump. A reinforcing member physically and electrically connects the exposed bump and the wiring line.Type: GrantFiled: October 23, 2009Date of Patent: March 6, 2012Assignee: Hynix Semiconductor Inc.Inventors: Woong Sun Lee, Qwan Ho Chung, Ki Young Kim
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Publication number: 20120015477Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Inventors: Woong Sun LEE, Qwan Ho CHUNG
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Publication number: 20110309504Abstract: A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines.Type: ApplicationFiled: May 31, 2011Publication date: December 22, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jin Ho BAE, Qwan Ho CHUNG, Woong Sun LEE
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Patent number: 8053879Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.Type: GrantFiled: October 30, 2008Date of Patent: November 8, 2011Assignee: Hynix Semiconductor Inc.Inventors: Woong Sun Lee, Qwan Ho Chung
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Publication number: 20110031604Abstract: A semiconductor package includes a semiconductor chip having a first surface, a second surface located opposite the first surface, and side surfaces connecting the first and second surfaces. The semiconductor chip includes bonding pads disposed on the first surface and having a molding member formed to cover the first surface of the semiconductor chip. The molding member is formed so as to expose the side surfaces of the semiconductor chip. The semiconductor chip also includes bonding members having first ends electrically connected to the respective bonding pads and second ends that are connected to and opposite the first ends. The second ends are exposed from side surfaces of the molding member after passing through the molding member so as to allow various electrical connections.Type: ApplicationFiled: October 23, 2009Publication date: February 10, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Ki Young KIM, Sung Ho HYUN, Myung Geun PARK, Woong Sun LEE
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Patent number: 7880093Abstract: A substrate for embodying multi-package comprises an underlying layer has a polymer material containing a conductive filler and provided with a step-like groove divided into step part and bottom part; a coating layer formed over the underlying layer, the coating layer is formed so that it may define a metal-wire forming area on the step part and the bottom part of the step-like groove and the conductive filler in the metal-wire forming area is exposed; and a metal wire formed via a plating process using the exposed conductive filler in the metal-wire forming area defined by the coating layer as a seed layer.Type: GrantFiled: March 29, 2007Date of Patent: February 1, 2011Assignee: Hynix Semiconductor Inc.Inventor: Woong Sun Lee
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Publication number: 20100326715Abstract: A circuit board includes a semiconductor chip having an upper surface and side surfaces connected to the upper surface. A bonding pad is disposed on the upper surface of the semiconductor chip. A bump is disposed on the bonding pad and projects from the bonding pad by a predetermined height. A circuit board body has a recess part, and the semiconductor chip is positioned in the recess part so that the circuit board body covers the upper surface and the side surfaces of the semiconductor chip while exposing an end of the bump. A wiring line is disposed on the circuit board body and part of the wiring line is positioned over the bump. An opening is formed in a portion of the part of the wiring line over the bump to expose the bump. A reinforcing member physically and electrically connects the exposed bump and the wiring line.Type: ApplicationFiled: October 23, 2009Publication date: December 30, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Woong Sun LEE, Qwan Ho CHUNG, Ki Young KIM
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Patent number: 7859108Abstract: A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.Type: GrantFiled: December 27, 2007Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventors: Woong Sun Lee, Il Hwan Cho, Myung Geun Park, Cheol Ho Joh, Eun Hye Do, Ki Young Kim, Ji Eun Kim, Jong Hyun Nam
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Publication number: 20100142118Abstract: A copper-clad laminate with a capacitor, a printed circuit board having the same and a semiconductor package having the printed circuit board are presented. The copper-clad laminate with the capacitor includes a first and second conductive layers, a film body, and thickness uniformity improving members. The first and second conductive layers are aligned to be substantially in parallel to each other and thus oppose each other. The film body is interposed between the first and the second conductive layer. The thickness uniformity improving members are also interposed between the first and second conductive layers and are inserted within the film body. The thickness uniformity improving members have one end connected to the first conductive layer and have the opposing ends connected to the second conductive layer.Type: ApplicationFiled: June 26, 2009Publication date: June 10, 2010Inventor: Woong Sun LEE