Patents by Inventor Woongrae Kim

Woongrae Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit
    Patent number: 11329651
    Abstract: An integrated circuit including: a clock generation circuit configured to generate first and second divided clock signals by dividing an external clock signal; and a command generation circuit configured to synchronize and decode an external command signal based on a divided clock signal of the first and second divided clock signals, which is synchronized with a chip select signal.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Electronic devices executing active operation
    Patent number: 11322186
    Abstract: An electronic device includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal, and a command/address signal and receives and outputs a first data and a second data. The semiconductor device is synchronized with the clock signal to receive or output the first data through a first memory region that is selected by the command/address signal when the chip selection signal and the command/address signal have a logic level combination to perform a first active operation. In addition, the semiconductor device is synchronized with the clock signal to receive or output the second data through the first memory region and a second memory region that are selected by the command/address signal based on the chip selection signal during a second active operation after the first active operation.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Devices adjusting a level of an active voltage supplied in a refresh operation
    Patent number: 11315621
    Abstract: A device includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyung Mook Kim, Woongrae Kim, Sang Il Park, Seung Hun Lee
  • Timing delay control circuits and electronic devices including the timing delay control circuits
    Patent number: 11308998
    Abstract: An electronic device includes a strobe signal generation circuit and a data output control circuit. The strobe signal generation circuit delays a mode register command by a first predetermined delay period to generate a mode register strobe signal during a mode register read operation. The strobe signal generation circuit adjusts a timing of the mode register strobe signal by detecting variation of timings of first and second variable delay mode register commands, which is generated based on the mode register command, during the mode register read operation. The data output control circuit delays an operation code, which is generated based on the mode register command, by a second predetermined delay period to generate a delayed operation code. The data output control circuit outputs the delayed operation code as data in synchronization with the mode register strobe signal.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Devices for performing a refresh operation based on power control operation
    Patent number: 11295799
    Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyung Mook Kim, Do Hong Kim, Woongrae Kim, Sang Il Park, Sang Woo Yoon, Jong Seok Han
  • POWER CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME AND POWER CONTROL METHOD OF SEMICONDUCTOR APPARATUS
    Publication number: 20220101907
    Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.
    Type: Application
    Filed: December 14, 2021
    Publication date: March 31, 2022
    Inventors: Woongrae KIM, Byeong Cheol LEE, Se Won LEE
  • DEVICES CONFIGURED TO CONDUCT A POWER GATING OPERATION
    Publication number: 20220094362
    Abstract: A device includes a power gating signal generation circuit, a clock interrupt signal generation circuit, and a shift clock generation circuit. The power gating signal generation circuit configured to generate a power gating signal based on a mode entry signal and a mode exit signal to perform a power gating operation. The clock interrupt signal generation circuit configured to generate a clock interrupt signal based on the mode entry signal and the power gating signal to perform a clock interrupt operation. The shift clock generation circuit configured to generate a shift clock signal supplied to an internal circuit based on the power gating signal and the clock interrupt signal.
    Type: Application
    Filed: March 8, 2021
    Publication date: March 24, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM
  • SEMICONDUCTOR DEVICE FOR STABLE CONTROL OF POWER-DOWN MODE
    Publication number: 20220084562
    Abstract: A semiconductor device includes: a first buffer circuit configured to receive a chip select signal in a power-down mode in response to a first select signal, a second buffer circuit configured to receive the chip select signal in an active mode in response to the first select signal, a power supply circuit configured to supply external power to a plurality of logic elements in the active mode in response to a second select signal, and not supply the external power to the plurality of logic elements in the power-down mode, and a select control circuit configured to transition a logic level of the second select signal at a first edge of a first chip select signal in the power-down mode, and then transition a logic level of the first select signal at a following second edge of the first chip select signal to exit from the power-down mode and enter the active mode.
    Type: Application
    Filed: January 15, 2021
    Publication date: March 17, 2022
    Inventor: Woongrae Kim
  • ELECTRONIC DEVICES CONTROLLING A POWER SUPPLY
    Publication number: 20220076719
    Abstract: An electronic device includes a control signal generation circuit and a control circuit. The control signal generation circuit is configured to generate a command power control signal, a status power control signal, an address power control signal, and a pre-charge power control signal which are enabled to control a supply of power voltages during a write operation and an auto-pre-charge operation. The control circuit is configured to receive the power voltages to generate a write signal, a write pre-charge signal, a bank address signal, an internal address signal, and an auto-pre-charge address signal based on an internal chip selection signal and an internal command/address signal while the command power control signal, the status power control signal, the address power control signal, and the pre-charge power control signal are enabled.
    Type: Application
    Filed: January 18, 2021
    Publication date: March 10, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM
  • Electronic devices controlling a power supply
    Patent number: 11270743
    Abstract: An electronic device includes a control signal generation circuit and a control circuit. The control signal generation circuit is configured to generate a command power control signal, a status power control signal, an address power control signal, and a pre-charge power control signal which are enabled to control a supply of power voltages during a write operation and an auto-pre-charge operation. The control circuit is configured to receive the power voltages to generate a write signal, a write pre-charge signal, a bank address signal, an internal address signal, and an auto-pre-charge address signal based on an internal chip selection signal and an internal command/address signal while the command power control signal, the status power control signal, the address power control signal, and the pre-charge power control signal are enabled.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • INTEGRATED CIRCUIT
    Publication number: 20220069825
    Abstract: An integrated circuit including: a clock generation circuit configured to generate first and second divided clock signals by dividing an external clock signal; and a command generation circuit configured to synchronize and decode an external command signal based on a divided clock signal of the first and second divided clock signals, which is synchronized with a chip select signal.
    Type: Application
    Filed: January 15, 2021
    Publication date: March 3, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM
  • Power control circuit, semiconductor apparatus including the same and power control method of semiconductor apparatus
    Patent number: 11264076
    Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Byeong Cheol Lee, Se Won Lee
  • TIMING DELAY CONTROL CIRCUITS AND ELECTRONIC DEVICES INCLUDING THE TIMING DELAY CONTROL CIRCUITS
    Publication number: 20220059143
    Abstract: An electronic device includes a strobe signal generation circuit and a data output control circuit. The strobe signal generation circuit delays a mode register command by a first predetermined delay period to generate a mode register strobe signal during a mode register read operation. The strobe signal generation circuit adjusts a timing of the mode register strobe signal by detecting variation of timings of first and second variable delay mode register commands, which is generated based on the mode register command, during the mode register read operation. The data output control circuit delays an operation code, which is generated based on the mode register command, by a second predetermined delay period to generate a delayed operation code. The data output control circuit outputs the delayed operation code as data in synchronization with the mode register strobe signal.
    Type: Application
    Filed: January 26, 2021
    Publication date: February 24, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM
  • ELECTRONIC DEVICES EXECUTING A TERMINATION OPERATION
    Publication number: 20220059145
    Abstract: An electronic device includes a termination control circuit and a data input/output (I/O) circuit. The termination control circuit is configured to generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed. In addition, the termination control circuit is configured to adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation. The data I/O circuit is configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed.
    Type: Application
    Filed: January 15, 2021
    Publication date: February 24, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM
  • ELECTRONIC DEVICES EXECUTING A TERMINATION OPERATION
    Publication number: 20220059146
    Abstract: An electronic device includes a write shift circuit configured to generate, when a write operation is performed, a period signal which is activated for a clock enable period, based on a write command in synchronization with a write clock signal. The electronic device also includes a clock generation circuit configured to generate, when the write operation is performed, the write clock signal based on the period signal. The electronic device further includes a termination control circuit configured to generate a termination enablement signal, based on the period signal in the write operation, which is activated for a termination operation period.
    Type: Application
    Filed: May 3, 2021
    Publication date: February 24, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM
  • ELECTRONIC DEVICES MITIGATING DEGRADATION OF MOS TRANSISTORS
    Publication number: 20220051715
    Abstract: An electronic device includes a flag generation circuit and a delay circuit. The flag generation circuit is configured to generate a flag signal, wherein a level of the flag signal changes based on a first internal command. The delay circuit is configured to generate a delay signal by delaying one of an operation signal and the flag signal by a predetermined period according to whether a predetermined operation is performed.
    Type: Application
    Filed: January 26, 2021
    Publication date: February 17, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM
  • SEMICONDUCTOR DEVICE
    Publication number: 20220044716
    Abstract: A semiconductor device includes an operation flag generation circuit configured to generate an operation flag at a time when a flag period elapses from a time when an internal setting signal is generated to perform a write operation accompanied by an auto-precharge operation; and an auto-precharge pulse generation circuit configured to generate an auto-precharge pulse by shifting the operation flag by a pulse generation period set by a period code based on divided clocks generated by dividing an internal clock.
    Type: Application
    Filed: March 8, 2021
    Publication date: February 10, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM
  • ELECTRONIC DEVICE CONFIGURED TO PERFORM AN AUTO-PRECHARGE OPERATION
    Publication number: 20220036930
    Abstract: An electronic device may include: an input/output control signal generation circuit configured to generate an input control signal and a first output control signal during a write operation, and generate a second output control signal during a write operation with an auto-precharge operation; and a bank address output circuit configured to latch a bank address based on the input control signal, and output the latched bank address as a write bank address for the write operation or a precharge bank address for the auto-precharge operation, based on the first output control signal and the second output control signal.
    Type: Application
    Filed: January 26, 2021
    Publication date: February 3, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM
  • Power gating system and electronic system including the same
    Patent number: 11237619
    Abstract: A power gating system may include a logic circuit area configured to perform a power-down operation according to at least one power-down control signal. The power gating system may also include a power gating control circuit configured to generate the at least one power-down control signal when a power-down request period is equal to or greater than a preset time according to a power-down mode signal.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • ELECTRONIC DEVICES CONFIGURED TO EXECUTE A BURST OPERATION
    Publication number: 20220020408
    Abstract: An electronic device includes a controller and a semiconductor device. The controller outputs a clock signal and data and successively outputs a chip selection signal and a command and address (command/address) signal for performing a write operation. The semiconductor device enters the write operation based on the chip selection signal and the command/address signal which are input in synchronization with the clock signal at a first point in time. In addition, the semiconductor device selectively performs one of a first burst operation and a second burst operation during the write operation based on the chip selection signal and the command/address signal which are input in synchronization with the clock signal at a second point in time, thereby storing the data into the semiconductor device.
    Type: Application
    Filed: October 26, 2020
    Publication date: January 20, 2022
    Applicant: SK hynix Inc.
    Inventor: Woongrae KIM