Abstract: A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.

Abstract: A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.

Abstract: A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.

Abstract: A memory controller includes a host interface configured to output at least one among a plurality of pieces of control information on the basis of data or a command received from a host. A lower-power mode entry controller is configured to select and output at least one among a plurality of control signals on the basis of at least one among the plurality of pieces of control information. The lower-power mode entry controller outputs the plurality of control signals to run a low-power mode in which power consumption is decreased. The plurality of pieces of control information include operation information representing a read operation or a write operation, pattern information representing a random operation or a sequential operation, and speed information representing a throughput of the host per unit time.

Abstract: A method is provided for performing a self-test on a memory device in a test mode, where the memory device includes a universal flash storage (UFS) link layer and a UFS physical layer having a transmitting unit and a receiving unit. The method includes generating a first signal; sending the first signal from a test unit through the UFS link layer to the transmitting unit in the UFS physical layer to be transmitted to the receiving unit; receiving a second signal at the test unit from the receiving unit in the UFS physical layer through the UFS link layer, the second signal being the first signal received by the receiving unit; and testing an operation performed by at least one of the UFS physical layer and the UFS link layer based on the first signal and the second signal.

Abstract: A method of controlling a power saving mode used in a serial advanced technology attachment (SATA) interface. The method of controlling a power saving mode used in a SATA interface for data transmission between a transmitter and a receiver includes: requesting the receiver to enter one of a plurality of power saving modes in a SATA protocol using the transmitter; and selecting one of the power saving modes using the receiver. In the method of controlling a power saving mode in a SATA interface, since a power saving mode can be selected independently of a power saving mode requested by a transmitter, a system can operate in a power saving mode that is suitable for the required properties of the system in accordance with a SATA protocol. Furthermore, the properties of the system required by a user can be realized by selecting a user-defined power saving mode.

Abstract: A cyclic redundancy check (CRC) management method performed in a serial advanced technology attachment (SATA) interface and a data storage device using the CRC management method. A host interface connected to the SATA interface performs CRC computation on transmitted data to generate a first CRC code, determines whether a host interface block error or a data integrity error occurs, or the status of a data storage device needs to be reported to the host interface, generates a second CRC code, which is different from the first CRC code, according to the determination result. If a frame including the transmitted data and the second CRC code is transmitted to a host, the host performs CRC computation on a data FIS in the transmitted data to expect the first CRC code. Since the CRC code in the transmitted data is the second CRC code, the host recognizes that the transmitted data is wrong and provides an error notification to the data storage device.

Abstract: Disclosed is a SATA device having self-testing function with an OOB-signaling operation and a method of testing the same. The SATA device includes target and test-signaling controllers that sequentially generate and transceive control signals for the OOB-signaling operation. The SATA device also includes a test flow controller regulating the flow of the OOB-signaling control signals, and an analogue signal processor generating and transceiving analogue signals in correspondence with the OOB-signaling control signals. The analogue signals transmitted from the analogue signal processor return to the input terminal through a feedback loop.

Abstract: A serial advanced technology attachment (SATA) device is provided. The SATA device includes a digital block and an analog black. The digital block is configured to generate and output an out-of-band (OOB) control signal. The analog block is configured to receive the OOB control signal, which has been output from the digital block, to receive the OOB control signal again after outputting it, and then output the OOB control signal to the digital block.

Abstract: A Universal Serial Bus/Serial Advanced Technology Attachment (USB/SATA) common interface Includes a USB/SATA common connector plug having a pin substrate, a plurality of USB contact terminals, and a plurality of SATA contact terminals. The pin substrate is formed of a non-conductive material. The USB contact terminals are formed in a first pattern on a first surface of the pin substrate. The SATA contact terminals are formed in a second pattern which is different from the first pattern, on a second surface of the pin substrate. Therefore, the USB/SATA common interface formed with the USB contact terminals and SATA contact terminals respectively having different patterns in a single plug or in a single socket reduces a layout size of a device and saves resources.

Abstract: A method of controlling a power saving mode used in a serial advanced technology attachment (SATA) interface. The method of controlling a power saving mode used in a SATA interface for data transmission between a transmitter and a receiver includes: requesting the receiver to enter one of a plurality of power saving modes in a SATA protocol using the transmitter; and selecting one of the power saving modes using the receiver. In the method of controlling a power saving mode in a SATA interface, since a power saving mode can be selected independently of a power saving mode requested by a transmitter, a system can operate in a power saving mode that is suitable for the required properties of the system in accordance with a SATA protocol. Furthermore, the properties of the system required by a user can be realized by selecting a user-defined power saving mode.

Abstract: Disclosed is a SATA device having self-testing function with an OOB-signaling operation and a method of testing the same. The SATA device includes target and test-signaling controllers that sequentially generate and transceive control signals for the OOB-signaling operation. The SATA device also includes a test flow controller regulating the flow of the OOB-signaling control signals, and an analogue signal processor generating and transceiving analogue signals in correspondence with the OOB-signaling control signals. The analogue signals transmitted from the analogue signal processor return to the input terminal through a feedback loop.