Abstract: A data receiving circuit is provided. The data receiving circuit includes a first transistor, a second transistor, a third transistor, and a latch circuit. The first transistor has a gate configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The second transistor has a gate configured to receive a first signal and a drain connected to the latch circuit. The third transistor has a gate configured to receive the first signal and a drain connected to the latch circuit. The second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal.

Abstract: The present application discloses a method for preparing a semiconductor device including an electronic fuse control circuit. The method includes providing a chip including an electronic fuse control circuit, wherein the electronic fuse control circuit includes a program voltage pad, a fuse element, a latch, a plurality of resistor selection pads, and a plurality of bonding option units. The method further includes providing a substrate including a first voltage bonding pad and a plurality of second voltage bonding pads, disposing the chip on the substrate, bonding the first voltage bonding pad to the program voltage pad, and bonding at least one of the plurality of second voltage bonding pads to at least one of the plurality of resistor selection pads.

Abstract: The present application discloses an electronic fuse control circuit, a semiconductor device and a method for forming a semiconductor device including an electronic fuse control circuit. The electronic fuse control circuit includes a program voltage pad, a fuse element, a latch, an operation switch unit, resistor selection pads, and bonding option units. The fuse element includes a first terminal coupled to the program voltage pad, and a second terminal. The operation switch unit forms an electrical connection between the second terminal of the fuse element and a ground terminal during a program operation, and forms an electrical connection between the second terminal of the fuse element and an input terminal of the latch during a read operation. Each of the bonding option units includes a resistor and a selection switch coupled in series between the input terminal of the latch and a resistor selection pad.

Abstract: A semiconductor package includes a package substrate, a semiconductor chip and a plurality of bonding wires. The package substrate includes a connection pad. The semiconductor chip is disposed over the package substrate and includes a chip pad, a bonding pad, and a redistribution layer. The bonding pad is closer to a periphery of the semiconductor chip than the chip pad. The redistribution layer is connected between the chip pad and the bonding pad. The bonding wires are connected in parallel between the connection pad and the bonding pad.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor die, a package substrate and bonding wires. The semiconductor die has I/O pads arranged at an active side. The package substrate is provided with a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and has an opening penetrating through the package substrate. The I/O pads are overlapped with the opening. A width of the opening at the second side of the package substrate is greater than a width of the opening at the first side of the package substrate. The bonding wires connect the I/O pads to the second side of the package substrate through the opening of the package substrate.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first substrate including a center region and an edge region distal from the center region, a first circuit layer positioned on the first substrate, a center power pad positioned in the first circuit layer and above the center region, an edge power pad positioned in the first circuit layer, above the edge region, and electrically coupled to the center power pad, a redistribution power pattern positioned above the first circuit layer and electrically coupled to the center power pad, and an edge power via positioned between the edge power pad and the redistribution power pattern, and electrically connecting the edge power pad and the redistribution power pattern. The first substrate, the center power pad, the edge power pad, the redistribution power pattern, and the edge power via together configure a first semiconductor die.

Abstract: A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and an equalizer. The data input circuit is configured to receive an input signal. The latch circuit is connected to the data input circuit and configured to output an output signal in response to the input signal. The equalizer is connected to the latch circuit and configured to provide a first voltage at a first node and a second voltage at a second node at an equalizing stage. The first voltage is different from the second voltage.

Abstract: A method includes following operations: a delay line delaying a first clock signal by a delay time to generate an output signal; a controller delaying the output signal by a first time interval to generate a first signal; the controller delaying the first clock signal by a second time interval shorter than the first time interval to generate a second clock signal; and the controller controlling the delay line according to the first signal and the second clock signal to adjust the delay time. A delay locked loop device is also disclosed herein.

Abstract: The present disclosure provides functional test equipment for a device under test and method of testing the device under test. The functional test equipment includes a first power supply, a second power supply and a relay system. The first power supply is configured to generate a first supply voltage. The second power supply is configured to generate a second supply voltage different from the first supply voltage. The relay system is configured to electrically couple the first power supply or the second power supply to the device under test, wherein the first supply voltage is applied to the device under test for a first duration and the second supply voltage is applied to the device under test for a second duration less than the first duration.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of fuse elements, a reference resistor unit, a first conductive terminal, a first switching circuit, and a second switching circuit. Each of the plurality of fuse elements has a first terminal and a second terminal. The reference resistor unit is configured to receive a first power signal and electrically couple with the first terminal of each of the plurality of fuse elements. The first conductive terminal is configured to receive a second power signal and is electrically connected to the second terminal of each of the plurality of fuse elements.

Abstract: A temperature delay device includes a first thermal sensor, a second thermal sensor, an inverter, and a latch circuit. The first thermal sensor is configured to measure a first temperature of a chip to output a first input signal. The second thermal sensor is configured to measure a second temperature of the chip to output a second input signal. The inverter is coupled to the first thermal sensor, and is configured to reverse the first input signal so as to output a third input signal. The latch circuit is coupled to the inverter and the second thermal sensor, and is configured to output an output signal according to the second input signal and the third input signal. The first temperature is different from the second temperature.

Abstract: The present disclosure provides a method of testing a testing device with a ground noise. The method includes coupling a device under test in series between a source and a ground in an automatic test equipment, coupling a ground bounce generator in series between the device under test and the ground, coupling the testing device to the device under test, providing a current by the source through the device under test and the ground bounce generator, controlling the ground bounce generator to generate the ground noise, and collecting a performance result of the testing device in the automatic test equipment.

Abstract: The present application provides a semiconductor die with decoupling capacitors and a manufacturing method of the semiconductor die. The semiconductor die includes first bonding pads, second bonding pads, bond metals and decoupling capacitors. The first bonding pads are coupled to a power supply voltage. The second bonding pads are coupled to a reference voltage. The bond metals are disposed on central portions of the first and second bonding pads. The decoupling capacitors are disposed under the first and second bonding pads, and overlapped with peripheral portions of the first and second bonding pads. The decoupling capacitors are in parallel connection with one another. First terminals of the decoupling capacitors are electrically connected to the first bonding pads, and second terminals of the decoupling capacitors are electrically connected to the second bonding pads.

Abstract: A electronic module includes a printed circuit board (PCB) substrate, a controller substrate, a controller, a memory device, and a heat spreader. The controller is disposed on the controller substrate. The memory device is disposed on the PCB substrate. The heat spreader is disposed on the controller and the memory device, in which the heat spreader has a first portion on the controller and a second portion on the memory device, and the heat spreader has a first opening between the first portion and the second portion.

Abstract: The present application provides a semiconductor package and a manufacturing method for the semiconductor package. The semiconductor package includes a package substrate, a first semiconductor die, a second semiconductor die, a first encapsulant and a second encapsulant. The package substrate has a first side and a second side facing away from the first side, and the second side has a concave recessed from a planar portion of the second side. The first semiconductor die is attached to the first side of the package substrate. The second semiconductor die is attached to a recessed surface of the concave. The first encapsulant covers the first side of the package substrate and encapsulates the first semiconductor die. The second encapsulant fills up the concave and encapsulates the second semiconductor die.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first substrate including a center region and an edge region distal from the center region, a first circuit layer positioned on the first substrate, a center power pad positioned in the first circuit layer and above the center region, an edge power pad positioned in the first circuit layer, above the edge region, and electrically coupled to the center power pad, a redistribution power pattern positioned above the first circuit layer and electrically coupled to the center power pad, and an edge power via positioned between the edge power pad and the redistribution power pattern, and electrically connecting the edge power pad and the redistribution power pattern. The first substrate, the center power pad, the edge power pad, the redistribution power pattern, and the edge power via together configure a first semiconductor die.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

Abstract: The present application provides a semiconductor package and a manufacturing method for the semiconductor package. The semiconductor package includes a package substrate, a first semiconductor die, a second semiconductor die, a first encapsulant and a second encapsulant. The package substrate has a first side and a second side facing away from the first side, and the second side has a concave recessed from a planar portion of the second side. The first semiconductor die is attached to the first side of the package substrate. The second semiconductor die is attached to a recessed surface of the concave. The first encapsulant covers the first side of the package substrate and encapsulates the first semiconductor die. The second encapsulant fills up the concave and encapsulates the second semiconductor die.

Abstract: The present application provides a method for manufacturing a semiconductor die. The method includes forming dielectric layers on a substrate; forming decoupling capacitors in the dielectric layers; forming first and second bonding pads on the dielectric layers, wherein the first bonding pads are coupled to a power supply voltage, the second bonding pads are coupled to a reference voltage, a group of the decoupling capacitors are located under one of the first bonding pads, first terminals of the group of the decoupling capacitors are electrically connected to the one of the first bonding pads, second terminals of the group of the decoupling capacitors are routed to one of the second bonding pads; and forming bond metals on the first and second bonding pads, wherein the decoupling capacitors are overlapped with the first and second bonding pads, and laterally surround portions of the dielectric layers overlapped with the bond metals.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.