Abstract: A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; gate structures and source/drain plugs over the base substrate; source/drain contact structures on the source/drain plugs; gate contact structures on the gate structures; and a dielectric layer on the gate structures and the source/drain plugs. Cavities are formed between the gate structures and the source/drain plugs along a surface of the base substrate. The dielectric layer encloses tops of the cavities.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate, a gate structure over the substrate, and a sidewall spacer structure located on a sidewall surface of the gate structure. The sidewall spacer structure includes a first sidewall spacer, a second sidewall spacer, and a cavity located between the first sidewall spacer and the second sidewall spacer. The first sidewall spacer is located on the sidewall surface of the gate structure. A top surface of the cavity is above a top surface of the gate structure, and a bottom surface of the cavity is coplanar with a bottom surface of the gate structure. The semiconductor structure also includes a source and drain plug located over the substrate on each side of the gate structure. The source and drain plug is located on a sidewall surface of the second sidewall spacer.

Abstract: A chemical mechanical planarization (CMP) apparatus is provided. The CMP apparatus includes at least one platen; and a polishing pad disposed on the platen. The CMP apparatus also includes a polishing head disposed above the platen and configured to clamp a to-be-polished wafer; and a basic solution supply port disposed above the platen and configured to supply a basic solution onto a surface of the polishing pad. Further, the CMP apparatus includes a slurry arm disposed above the platen and configured to supply a polish slurry on the surface of the polishing pad; and a deionized water supply port configured to supply deionized water onto the surface of the polishing pad. Further, the CMP apparatus also includes a negative power source configured to apply a negative voltage onto the surface of the polishing pad.

Abstract: A chemical mechanical planarization (CMP) apparatus is provided. The CMP apparatus includes at least one platen; and a polishing pad disposed on the platen. The CMP apparatus also includes a polishing head disposed above the platen and configured to clamp a to-be-polished wafer; and a basic solution supply port disposed above the platen and configured to supply a basic solution onto a surface of the polishing pad. Further, the CMP apparatus includes a slurry arm disposed above the platen and configured to supply a polish slurry on the surface of the polishing pad; and a deionized water supply port configured to supply deionized water onto the surface of the polishing pad. Further, the CMP apparatus also includes a negative power source configured to apply a negative voltage onto the surface of the polishing pad.

Abstract: A chemical mechanical polishing method includes providing a device layer having a surface to be polished, polishing the surface using an alkaline grinding slurry, removing a residual layer that is been formed on the polished surface using an acid buffer, forming a passivation layer covering the polished surface of the device layer after the residual layer has been removed, and cleaning the passivation layer using deionized water. A semiconductor device thus fabricated has surfaces with excellent flatness, good manufacturing yield and long-term reliability.

Abstract: A chemical mechanical polishing method includes providing a device layer having a surface to be polished, polishing the surface using an alkaline grinding slurry, removing a residual layer that is been formed on the polished surface using an acid buffer, forming a passivation layer covering the polished surface of the device layer after the residual layer has been removed, and cleaning the passivation layer using deionized water. A semiconductor device thus fabricated has surfaces with excellent flatness, good manufacturing yield and long-term reliability.

Abstract: A Chemical Mechanical Polishing (CMP) method includes providing a semiconductor substrate having an overlying dielectric layer, performing a first grinding on the dielectric layer, wherein the first grinding produces organic residues on a surface of the dielectric layer after the first grinding. The method further includes performing a second grinding on the dielectric layer by using an alkaline solution to remove the organic residues on the surface of the dielectric layer. The organic residues remaining on the surface of the dielectric layer are removed by using the alkaline solution after the first grinding process is performed. The method additionally includes cleaning a grinding pad and the substrate using deionized water.

Abstract: A chemical mechanical polishing method includes providing a semiconductor substrate having a dielectric layer formed thereon, wherein the dielectric layer includes vias and/or grooves, forming a stop layer on the dielectric layer and on sidewalls and bottoms of the vias and/or grooves; forming a metal layer on the stop layer, which completely fills the vias and/or grooves. The method further includes grinding the metal layer until the stop layer is exposed, removing a portion of the stop layer with a first grinding slurry, and removing the stop layer left over with a second grinding slurry until the dielectric layer is exposed, wherein a quantity and a diameter of oxide grinding particles in the second grinding slurry are smaller than those in the first grinding slurry. The method guarantees a removal rate that is equal to conventional art and prevents damage to the wafer so that the products thus made have an improved quality and performance.