Patents by Inventor Wuping Liu
Wuping Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7276440Abstract: In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.Type: GrantFiled: December 12, 2003Date of Patent: October 2, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Fan Zhang, Bei Chao Zhang, Wuping Liu, Kho Liep Chok, Liang Choo Hsia, Tae Jong Lee, Juan Boon Tan, Xian Bin Wang
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Patent number: 7256136Abstract: In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.Type: GrantFiled: February 2, 2006Date of Patent: August 14, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wuping Liu, Bei Chao Zhang, Liang Choo Hsia
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Publication number: 20070134941Abstract: An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.Type: ApplicationFiled: December 8, 2005Publication date: June 14, 2007Inventors: Huang Liu, Bei Zhang, Wuping Liu, John Sudijono, Liang Hsia
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Patent number: 7153766Abstract: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material.Type: GrantFiled: January 9, 2003Date of Patent: December 26, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Beichao Zhang, Wuping Liu, Liang-Choo Hsia
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Publication number: 20060128156Abstract: In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.Type: ApplicationFiled: February 2, 2006Publication date: June 15, 2006Inventors: Wuping Liu, Bei Zhang, Liang Hsia
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Publication number: 20060088995Abstract: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material.Type: ApplicationFiled: December 12, 2005Publication date: April 27, 2006Inventors: Beichao Zhang, Wuping Liu, Liang-Choo Hsia
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Patent number: 7012022Abstract: In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.Type: GrantFiled: October 30, 2003Date of Patent: March 14, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wuping Liu, Bei Chao Zhang, Liang Choo Hsia
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Patent number: 6995087Abstract: An integrated circuit manufacturing method includes providing a base, forming a first conductor, forming a first barrier layer, forming a first dielectric layer, and forming a masking layer. The method further including forming a first via opening in the masking layer, forming a first trench opening in the masking layer, and simultaneously forming a second via opening in a layer under the masking layer, and forming a second trench opening through the masking layer and in the layer under the masking layer and simultaneously forming a third via opening in another layer under the masking layer. The method further including removing the first barrier layer using the third via opening and the masking layer to form a trench and a via, and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.Type: GrantFiled: December 23, 2002Date of Patent: February 7, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Wuping Liu, Juan Boon Tan, Bei Chao Zhang, Alan Cuthbertson
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Publication number: 20060003573Abstract: An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.Type: ApplicationFiled: July 5, 2005Publication date: January 5, 2006Inventors: Yeow Lim, Wuping Liu, Tae Lee, Bei Zhang, Juan Boon Tan, Alan Cuthbertson, Chin Neo
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Patent number: 6967156Abstract: A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks.Type: GrantFiled: October 22, 2003Date of Patent: November 22, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yeow Kheng Lim, Wuping Liu, Tae Jong Lee, Bei Chao Zhang, Juan Boon Tan, Alan Cuthbertson, Chin Chuan Neo
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Publication number: 20050191851Abstract: A new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation of a cap of barrier material, conventional concerns of copper oxidation, copper back-sputtering and the like are eliminated.Type: ApplicationFiled: April 29, 2005Publication date: September 1, 2005Inventors: Wuping Liu, Beichao Zhang, Liang Hsia
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Publication number: 20050127495Abstract: In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.Type: ApplicationFiled: December 12, 2003Publication date: June 16, 2005Inventors: Fan Zhang, Bei Zhang, Wuping Liu, Kho Chok, Liang Hsia, Tae Lee, Juan Tan, Xian Wang
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Publication number: 20050093158Abstract: In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.Type: ApplicationFiled: October 30, 2003Publication date: May 5, 2005Inventors: Wuping Liu, Bei Zhang, Liang Hsia
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Publication number: 20050090095Abstract: A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A structure having a metal structure formed thereover is provided. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. The upper dielectric layer is patterned to form an opening exposing a portion of the underlying middle dielectric material layer. The opening having a width. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. The middle dielectric material layer opening exposing a portion of the middle etch stop layer.Type: ApplicationFiled: October 22, 2003Publication date: April 28, 2005Inventors: Yeow Lim, Wuping Liu, Tae Lee, Bei Zhang, Juan Tan, Alan Cuthbertson, Chin Neo
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Publication number: 20040137709Abstract: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material.Type: ApplicationFiled: January 9, 2003Publication date: July 15, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Beichao Zhang, Wuping Liu, Liang-Choo Hsia
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Publication number: 20040121585Abstract: An integrated circuit manufacturing method includes providing a base, forming a first conductor, forming a first barrier layer, forming a first dielectric layer, and forming a masking layer. The method further including forming a first via opening in the masking layer, forming a first trench opening in the masking layer, and simultaneously forming a second via opening in a layer under the masking layer, and forming a second trench opening through the masking layer and in the layer under the masking layer and simultaneously forming a third via opening in another layer under the masking layer. The method further including removing the first barrier layer using the third via opening and the masking layer to form a trench and a via, and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Wuping Liu, Juan Boon Tan, Bei Chao Zhang, Alan Cuthbertson
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Publication number: 20040048468Abstract: A new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation of a cap of barrier material, conventional concerns of copper oxidation, copper back-sputtering and the like are eliminated.Type: ApplicationFiled: September 10, 2002Publication date: March 11, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Wuping Liu, Beichao Zhang, Liang Choo Hsia