Patents by Inventor Wuu-Cherng Lin

Wuu-Cherng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10043716
    Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 7, 2018
    Assignee: Altera Corporation
    Inventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
  • Publication number: 20160358825
    Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Applicant: Altera Corporation
    Inventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
  • Patent number: 9449962
    Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: September 20, 2016
    Assignee: Altera Corporation
    Inventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
  • Patent number: 8921217
    Abstract: Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: December 30, 2014
    Assignee: Altera Corporation
    Inventors: Wuu-Cherng Lin, Fangyun Richter, Che Ta Hsu, Wen Sun Wu
  • Publication number: 20130157451
    Abstract: Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 20, 2013
    Inventors: Wuu-Cherng Lin, Fangyun Richter, Che Ta Hsu, Wen Sun Wu
  • Publication number: 20130140640
    Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
    Type: Application
    Filed: August 4, 2011
    Publication date: June 6, 2013
    Applicant: ALTERA CORPORATION
    Inventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin
  • Publication number: 20120261738
    Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Inventors: Dustin Do, Andy Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
  • Patent number: 8217464
    Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: July 10, 2012
    Assignee: Altera Corporation
    Inventors: Dustin Do, Andy L. Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White
  • Publication number: 20120032276
    Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 9, 2012
    Applicant: Altera Corporation
    Inventors: Dustin Do, Andy Lee, Giles V. Powell, Bradley Jensen, Swee Aun Lau, Wuu-Cherng Lin, Thomas H. White